WebSVN – HelenOS – Diff – /branches/network/kernel/arch/mips32/include/atomic.h


/*
 * Copyright (c) 2005 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32 
 * @{
 */
/** @file
 */
 
#ifndef KERN_mips32_ATOMIC_H_
#define KERN_mips32_ATOMIC_H_
 
#define atomic_inc(x)  ((void) atomic_add(x, 1))
#define atomic_dec(x)  ((void) atomic_add(x, -1))
 
#define atomic_postinc(x)  (atomic_add(x, 1) - 1)
#define atomic_postdec(x)  (atomic_add(x, -1) + 1)
 
#define atomic_preinc(x)  atomic_add(x, 1)
#define atomic_predec(x)  atomic_add(x, -1)
 
/* Atomic addition of immediate value.
 *
 * @param val Memory location to which will be the immediate value added.
 * @param i Signed immediate that will be added to *val.
 *
 * @return Value after addition.
 */
static inline long atomic_add(atomic_t *val, int i)
{
    long tmp, v;
   
    asm volatile (
        "1:\n"
        "   ll %0, %1\n"
        "   addu %0, %0, %3\n"  /* same as addi, but never traps on overflow */
        "   move %2, %0\n"
        "   sc %0, %1\n"
        "   beq %0, %4, 1b\n"   /* if the atomic operation failed, try again */
        "   nop\n"
        : "=&r" (tmp), "+m" (val->count), "=&r" (v)
        : "r" (i), "i" (0)
    );
   
    return v;
}
 
static inline uint32_t test_and_set(atomic_t *val) {
    uint32_t tmp, v;
   
    asm volatile (
        "1:\n"
        "   ll %2, %1\n"
        "   bnez %2, 2f\n"
        "   li %0, %3\n"
        "   sc %0, %1\n"
        "   beqz %0, 1b\n"
        "2:\n"
        : "=&r" (tmp), "+m" (val->count), "=&r" (v)
        : "i" (1)
    );
   
    return v;
}
 
static inline void atomic_lock_arch(atomic_t *val) {
    do {
        while (val->count)
            ;
    } while (test_and_set(val));
}
 
#endif
 
/** @}
 */
 

Rev 4153	Rev 4718
1	/*	1	/*
2	* Copyright (c) 2005 Ondrej Palkovsky	2	* Copyright (c) 2005 Ondrej Palkovsky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32	29	/** @addtogroup mips32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_mips32_ATOMIC_H_	35	#ifndef KERN_mips32_ATOMIC_H_
36	#define KERN_mips32_ATOMIC_H_	36	#define KERN_mips32_ATOMIC_H_
37		37
38	#define atomic_inc(x) ((void) atomic_add(x, 1))	38	#define atomic_inc(x) ((void) atomic_add(x, 1))
39	#define atomic_dec(x) ((void) atomic_add(x, -1))	39	#define atomic_dec(x) ((void) atomic_add(x, -1))
40		40
41	#define atomic_postinc(x) (atomic_add(x, 1) - 1)	41	#define atomic_postinc(x) (atomic_add(x, 1) - 1)
42	#define atomic_postdec(x) (atomic_add(x, -1) + 1)	42	#define atomic_postdec(x) (atomic_add(x, -1) + 1)
43		43
44	#define atomic_preinc(x) atomic_add(x, 1)	44	#define atomic_preinc(x) atomic_add(x, 1)
45	#define atomic_predec(x) atomic_add(x, -1)	45	#define atomic_predec(x) atomic_add(x, -1)
46		46
47	/* Atomic addition of immediate value.	47	/* Atomic addition of immediate value.
48	*	48	*
49	* @param val Memory location to which will be the immediate value added.	49	* @param val Memory location to which will be the immediate value added.
50	* @param i Signed immediate that will be added to *val.	50	* @param i Signed immediate that will be added to *val.
51	*	51	*
52	* @return Value after addition.	52	* @return Value after addition.
53	*/	53	*/
54	static inline long atomic_add(atomic_t *val, int i)	54	static inline long atomic_add(atomic_t *val, int i)
55	{	55	{
56	long tmp, v;	56	long tmp, v;
57		57
58	asm volatile (	58	asm volatile (
59	"1:\n"	59	"1:\n"
60	" ll %0, %1\n"	60	" ll %0, %1\n"
61	" addu %0, %0, %3\n" /* same as addi, but never traps on overflow */	61	" addu %0, %0, %3\n" /* same as addi, but never traps on overflow */
62	" move %2, %0\n"	62	" move %2, %0\n"
63	" sc %0, %1\n"	63	" sc %0, %1\n"
64	" beq %0, %4, 1b\n" /* if the atomic operation failed, try again */	64	" beq %0, %4, 1b\n" /* if the atomic operation failed, try again */
65	" nop\n"	65	" nop\n"
66	: "=&r" (tmp), "+m" (val->count), "=&r" (v)	66	: "=&r" (tmp), "+m" (val->count), "=&r" (v)
67	: "r" (i), "i" (0)	67	: "r" (i), "i" (0)
68	);	68	);
69		69
70	return v;	70	return v;
71	}	71	}
72		72
73	static inline uint32_t test_and_set(atomic_t *val) {	73	static inline uint32_t test_and_set(atomic_t *val) {
74	uint32_t tmp, v;	74	uint32_t tmp, v;
75		75
76	asm volatile (	76	asm volatile (
77	"1:\n"	77	"1:\n"
78	" ll %2, %1\n"	78	" ll %2, %1\n"
79	" bnez %2, 2f\n"	79	" bnez %2, 2f\n"
80	" li %0, %3\n"	80	" li %0, %3\n"
81	" sc %0, %1\n"	81	" sc %0, %1\n"
82	" beqz %0, 1b\n"	82	" beqz %0, 1b\n"
83	"2:\n"	83	"2:\n"
84	: "=&r" (tmp), "+m" (val->count), "=&r" (v)	84	: "=&r" (tmp), "+m" (val->count), "=&r" (v)
85	: "i" (1)	85	: "i" (1)
86	);	86	);
87		87
88	return v;	88	return v;
89	}	89	}
90		90
-		91	static inline void atomic_lock_arch(atomic_t *val) {
-		92	do {
-		93	while (val->count)
-		94	;
-		95	} while (test_and_set(val));
-		96	}
-		97
91	#endif	98	#endif
92		99
93	/** @}	100	/** @}
94	*/	101	*/
95		102

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(root)/branches/network/kernel/arch/mips32/include/atomic.h – Rev 4153 → 4718