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Rev 4153 Rev 4581
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{
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{
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    tlb_invalidate_all();
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    tlb_invalidate_all();
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}
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}
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void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
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void tlb_invalidate_pages(asid_t asid, uintptr_t page, size_t cnt)
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{
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{
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    region_register rr;
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    region_register rr;
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    bool restore_rr = false;
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    bool restore_rr = false;
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    int b = 0;
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    int b = 0;
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    int c = cnt;
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    int c = cnt;
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 * @param entry     The rest of TLB entry as required by TLB insertion
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 * @param entry     The rest of TLB entry as required by TLB insertion
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 *          format.
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 *          format.
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 * @param tr        Translation register.
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 * @param tr        Translation register.
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 */
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 */
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void
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void
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itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
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itr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
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{
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{
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    tr_mapping_insert(va, asid, entry, false, tr);
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    tr_mapping_insert(va, asid, entry, false, tr);
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}
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}
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/** Insert data into data translation register.
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/** Insert data into data translation register.
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 * @param entry     The rest of TLB entry as required by TLB insertion
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 * @param entry     The rest of TLB entry as required by TLB insertion
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 *          format.
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 *          format.
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 * @param tr        Translation register.
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 * @param tr        Translation register.
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 */
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 */
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void
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void
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dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, index_t tr)
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dtr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, size_t tr)
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{
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{
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    tr_mapping_insert(va, asid, entry, true, tr);
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    tr_mapping_insert(va, asid, entry, true, tr);
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}
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}
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/** Insert data into instruction or data translation register.
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/** Insert data into instruction or data translation register.
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 *          instruction translation register otherwise.
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 *          instruction translation register otherwise.
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 * @param tr        Translation register.
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 * @param tr        Translation register.
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 */
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 */
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void
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void
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tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
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tr_mapping_insert(uintptr_t va, asid_t asid, tlb_entry_t entry, bool dtr,
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    index_t tr)
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    size_t tr)
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{
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{
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    region_register rr;
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    region_register rr;
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    bool restore_rr = false;
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    bool restore_rr = false;
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    rr.word = rr_read(VA2VRN(va));
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    rr.word = rr_read(VA2VRN(va));
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 *          translation cache otherwise.
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 *          translation cache otherwise.
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 * @param tr        Translation register if dtr is true, ignored otherwise.
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 * @param tr        Translation register if dtr is true, ignored otherwise.
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 */
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 */
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void
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void
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dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
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dtlb_kernel_mapping_insert(uintptr_t page, uintptr_t frame, bool dtr,
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    index_t tr)
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    size_t tr)
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{
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{
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    tlb_entry_t entry;
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    tlb_entry_t entry;
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    entry.word[0] = 0;
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    entry.word[0] = 0;
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    entry.word[1] = 0;
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    entry.word[1] = 0;
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 * Purge DTR entries used by the kernel.
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 * Purge DTR entries used by the kernel.
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 *
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 *
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 * @param page      Virtual page address including VRN bits.
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 * @param page      Virtual page address including VRN bits.
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 * @param width     Width of the purge in bits.
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 * @param width     Width of the purge in bits.
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 */
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 */
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void dtr_purge(uintptr_t page, count_t width)
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void dtr_purge(uintptr_t page, size_t width)
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{
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{
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    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
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    asm volatile ("ptr.d %0, %1\n" : : "r" (page), "r" (width << 2));
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}
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}
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