WebSVN – HelenOS – Diff – /branches/network/kernel/arch/ia64/src/ivt.S



#
# Copyright (C) 2005 Jakub Vana
# Copyright (C) 2005 Jakub Jermar
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:

# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
 
#include <arch/stack.h>
#include <arch/register.h>
 
#define STACK_ITEMS		12
#define STACK_FRAME_SIZE	((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
 
#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)

	
	mov r27 = ar.rnat
	mov r28 = ar.bspstore ;;
	
	/* assume kernel backing store */
	/* mov ar.bspstore = r28 ;; */
	
	mov r29 = ar.bsp
	
	st8 [r31] = r27, -8 ;;	/* save ar.rnat */
	st8 [r31] = r28, -8 ;;	/* save ar.bspstore */

	ld8 r27 = [r31], +8 ;;		/* load ar.rnat */
	ld8 r26 = [r31], +8 ;;		/* load cr.ifs */
	ld8 r25 = [r31], +8 ;;		/* load ar.pfs */
	ld8 r24 = [r31], +8 ;;		/* load ar.rsc */
 
	/* mov ar.bspstore = r28 ;; */	/* (step 4) */
	/* mov ar.rnat = r27 */		/* (step 5) */
 
	mov ar.pfs = r25		/* (step 6) */
	mov cr.ifs = r26	
 
	mov ar.rsc = r24		/* (step 7) */

	mov out0 = r26
	
	add out1 = STACK_SCRATCH_AREA_SIZE, r12
 
    /* 6. switch to bank 1 and reenable PSR.ic */
	ssm PSR_IC_MASK
	bsw.1 ;;
	srlz.d
	
    /* 7. preserve branch and application registers */
    	mov loc3 = ar.unat

	mov loc44 = r29
	mov loc45 = r30
	mov loc46 = r31
    
    /* 9. skipped (will not enable interrupts) */
	/*
    	 * ssm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 10. call handler */
    	mov b1 = loc2
	br.call.sptk.many b0 = b1
 
    /* 11. return from handler */
0:
	
    /* 12. skipped (will not disable interrupts) */
	/*
    	 * rsm PSR_I_MASK
	 * ;;
	 * srlz.d
	 */
 
    /* 13. restore general and floating-point registers */
	/* TODO: restore floating-point context */
	mov r1 = loc17
	mov r2 = loc18

	mov b5 = loc14
	mov b6 = loc15
	mov b7 = loc16
	
    /* 15. disable PSR.ic and switch to bank 0 */
	rsm PSR_IC_MASK
	bsw.0 ;;
	srlz.d
 
	mov r24 = loc1
	mov ar.pfs = loc0

Rev 477	Rev 478
Line 1...	Line 1...
1	#	1	#
2	# Copyright (C) 2005 Jakub Vana	2	# Copyright (C) 2005 Jakub Vana
-		3	# Copyright (C) 2005 Jakub Jermar
3	# All rights reserved.	4	# All rights reserved.
4	#	5	#
5	# Redistribution and use in source and binary forms, with or without	6	# Redistribution and use in source and binary forms, with or without
6	# modification, are permitted provided that the following conditions	7	# modification, are permitted provided that the following conditions
7	# are met:	8	# are met:
Line 25...	Line 26...
25	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	#	28	#
28		29
29	#include <arch/stack.h>	30	#include <arch/stack.h>
-		31	#include <arch/register.h>
30		32
31	#define STACK_ITEMS 12	33	#define STACK_ITEMS 12
32	#define STACK_FRAME_SIZE ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)	34	#define STACK_FRAME_SIZE ((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
33		35
34	#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)	36	#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
Line 102...	Line 104...
102		104
103	mov r27 = ar.rnat	105	mov r27 = ar.rnat
104	mov r28 = ar.bspstore ;;	106	mov r28 = ar.bspstore ;;
105		107
106	/* assume kernel backing store */	108	/* assume kernel backing store */
107	mov ar.bspstore = r28 ;;	109	/* mov ar.bspstore = r28 ;; */
108		110
109	mov r29 = ar.bsp	111	mov r29 = ar.bsp
110		112
111	st8 [r31] = r27, -8 ;; /* save ar.rnat */	113	st8 [r31] = r27, -8 ;; /* save ar.rnat */
112	st8 [r31] = r28, -8 ;; /* save ar.bspstore */	114	st8 [r31] = r28, -8 ;; /* save ar.bspstore */
Line 142...	Line 144...
142	ld8 r27 = [r31], +8 ;; /* load ar.rnat */	144	ld8 r27 = [r31], +8 ;; /* load ar.rnat */
143	ld8 r26 = [r31], +8 ;; /* load cr.ifs */	145	ld8 r26 = [r31], +8 ;; /* load cr.ifs */
144	ld8 r25 = [r31], +8 ;; /* load ar.pfs */	146	ld8 r25 = [r31], +8 ;; /* load ar.pfs */
145	ld8 r24 = [r31], +8 ;; /* load ar.rsc */	147	ld8 r24 = [r31], +8 ;; /* load ar.rsc */
146		148
147	mov ar.bspstore = r28 ;; /* (step 4) */	149	/* mov ar.bspstore = r28 ;; / / (step 4) */
148	mov ar.rnat = r27 /* (step 5) */	150	/* mov ar.rnat = r27 / / (step 5) */
149		151
150	mov ar.pfs = r25 /* (step 6) */	152	mov ar.pfs = r25 /* (step 6) */
151	mov cr.ifs = r26	153	mov cr.ifs = r26
152		154
153	mov ar.rsc = r24 /* (step 7) */	155	mov ar.rsc = r24 /* (step 7) */
Line 187...	Line 189...
187	mov out0 = r26	189	mov out0 = r26
188		190
189	add out1 = STACK_SCRATCH_AREA_SIZE, r12	191	add out1 = STACK_SCRATCH_AREA_SIZE, r12
190		192
191	/* 6. switch to bank 1 and reenable PSR.ic */	193	/* 6. switch to bank 1 and reenable PSR.ic */
192	ssm 0x2000	194	ssm PSR_IC_MASK
193	bsw.1 ;;	195	bsw.1 ;;
194	srlz.d	196	srlz.d
195		197
196	/* 7. preserve branch and application registers */	198	/* 7. preserve branch and application registers */
197	mov loc3 = ar.unat	199	mov loc3 = ar.unat
Line 243...	Line 245...
243	mov loc44 = r29	245	mov loc44 = r29
244	mov loc45 = r30	246	mov loc45 = r30
245	mov loc46 = r31	247	mov loc46 = r31
246		248
247	/* 9. skipped (will not enable interrupts) */	249	/* 9. skipped (will not enable interrupts) */
-		250	/*
-		251	* ssm PSR_I_MASK
-		252	* ;;
-		253	* srlz.d
-		254	*/
248		255
249	/* 10. call handler */	256	/* 10. call handler */
250	mov b1 = loc2	257	mov b1 = loc2
251	br.call.sptk.many b0 = b1	258	br.call.sptk.many b0 = b1
252		259
253	/* 11. return from handler */	260	/* 11. return from handler */
254	0:	261	0:
255		262
256	/* 12. skipped (will not disable interrupts) */	263	/* 12. skipped (will not disable interrupts) */
-		264	/*
-		265	* rsm PSR_I_MASK
-		266	* ;;
-		267	* srlz.d
-		268	*/
257		269
258	/* 13. restore general and floating-point registers */	270	/* 13. restore general and floating-point registers */
259	/* TODO: restore floating-point context */	271	/* TODO: restore floating-point context */
260	mov r1 = loc17	272	mov r1 = loc17
261	mov r2 = loc18	273	mov r2 = loc18
Line 305...	Line 317...
305	mov b5 = loc14	317	mov b5 = loc14
306	mov b6 = loc15	318	mov b6 = loc15
307	mov b7 = loc16	319	mov b7 = loc16
308		320
309	/* 15. disable PSR.ic and switch to bank 0 */	321	/* 15. disable PSR.ic and switch to bank 0 */
310	rsm 0x2000	322	rsm PSR_IC_MASK
311	bsw.0 ;;	323	bsw.0 ;;
312	srlz.d	324	srlz.d
313		325
314	mov r24 = loc1	326	mov r24 = loc1
315	mov ar.pfs = loc0	327	mov ar.pfs = loc0

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(root)/branches/network/kernel/arch/ia64/src/ivt.S @ 4718 – Rev 477 → 478