WebSVN – HelenOS – Diff – /branches/fs/kernel/arch/sparc64/src/mm/tlb.c

 #ifdef CONFIG_TSB
 #include <arch/mm/tsb.h>
 #endif
-static void dtlb_pte_copy(pte_t *t, bool ro);
+static void dtlb_pte_copy(pte_t *t, index_t index, bool ro);
-static void itlb_pte_copy(pte_t *t);
+static void itlb_pte_copy(pte_t *t, index_t index);
-static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const
+static void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
-    char *str);
+    const char *str);
 static void do_fast_data_access_mmu_miss_fault(istate_t *istate,
-     tlb_tag_access_reg_t tag, const char *str);
+    tlb_tag_access_reg_t tag, const char *str);
 static void do_fast_data_access_protection_fault(istate_t *istate,
     tlb_tag_access_reg_t tag, const char *str);
 char *context_encoding[] = {
     "Primary",
     "Secondary",
     "Nucleus",
  * @param frame Physical frame address.
  * @param pagesize Page size.
  * @param locked True for permanent mappings, false otherwise.
  * @param cacheable True if the mapping is cacheable, false otherwise.
  */
-void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize, bool
+void dtlb_insert_mapping(uintptr_t page, uintptr_t frame, int pagesize,
-    locked, bool cacheable)
+    bool locked, bool cacheable)
+{
     tlb_tag_access_reg_t tag;
     tlb_data_t data;
     page_address_t pg;
     frame_address_t fr;
     dtlb_data_in_write(data.value);
+}
 /** Copy PTE to TLB.
+ *
- * @param t Page Table Entry to be copied.
+ * @param t     Page Table Entry to be copied.
+ * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
- * @param ro If true, the entry will be created read-only, regardless of its w
+ * @param ro    If true, the entry will be created read-only, regardless of its
- *  field.
+ *      w field.
  */
-void dtlb_pte_copy(pte_t *t, bool ro)
+void dtlb_pte_copy(pte_t *t, index_t index, bool ro)
+{
     tlb_tag_access_reg_t tag;
     tlb_data_t data;
     page_address_t pg;
     frame_address_t fr;
-    pg.address = t->page;
+    pg.address = t->page + (index << MMU_PAGE_WIDTH);
-    fr.address = t->frame;
+    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
     tag.value = 0;
     tag.context = t->as->asid;
     tag.vpn = pg.vpn;
     dtlb_tag_access_write(tag.value);
     data.value = 0;
     data.v = true;
     data.size = PAGESIZE_8K;
     data.pfn = fr.pfn;
     data.l = false;
     data.cv = t->c;
 #endif /* CONFIG_VIRT_IDX_DCACHE */
     data.p = t->k;      /* p like privileged */
     data.w = ro ? false : t->w;
     data.g = t->g;
     dtlb_data_in_write(data.value);
+}
 /** Copy PTE to ITLB.
+ *
- * @param t Page Table Entry to be copied.
+ * @param t     Page Table Entry to be copied.
+ * @param index Zero if lower 8K-subpage, one if higher 8K-subpage.
  */
-void itlb_pte_copy(pte_t *t)
+void itlb_pte_copy(pte_t *t, index_t index)
+{
     tlb_tag_access_reg_t tag;
     tlb_data_t data;
     page_address_t pg;
     frame_address_t fr;
-    pg.address = t->page;
+    pg.address = t->page + (index << MMU_PAGE_WIDTH);
-    fr.address = t->frame;
+    fr.address = t->frame + (index << MMU_PAGE_WIDTH);
     tag.value = 0;
     tag.context = t->as->asid;
     tag.vpn = pg.vpn;
     itlb_data_in_write(data.value);
+}
 /** ITLB miss handler. */
-void fast_instruction_access_mmu_miss(int n, istate_t *istate)
+void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate)
+{
     uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE);
+    index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE;
     pte_t *t;
     page_table_lock(AS, true);
     t = page_mapping_find(AS, va);
     if (t && PTE_EXECUTABLE(t)) {
         /*
          * The mapping was found in the software page hash table.
          * Insert it into ITLB.
          */
         t->a = true;
-        itlb_pte_copy(t);
+        itlb_pte_copy(t, index);
 #ifdef CONFIG_TSB
-        itsb_pte_copy(t);
+        itsb_pte_copy(t, index);
 #endif
         page_table_unlock(AS, true);
     } else {
         /*
          * Forward the page fault to the address space page fault
          * handler.
          */
         page_table_unlock(AS, true);
         if (as_page_fault(va, PF_ACCESS_EXEC, istate) == AS_PF_FAULT) {
             do_fast_instruction_access_mmu_miss_fault(istate,
                 __FUNCTION__);
+        }
+    }
+}
 /** DTLB miss handler.
+ *
  * Note that some faults (e.g. kernel faults) were already resolved by the
  * low-level, assembly language part of the fast_data_access_mmu_miss handler.
+ *
+ * @param tag Content of the TLB Tag Access register as it existed when the
+ *    trap happened. This is to prevent confusion created by clobbered
+ *    Tag Access register during a nested DTLB miss.
+ * @param istate Interrupted state saved on the stack.
  */
-void fast_data_access_mmu_miss(int n, istate_t *istate)
+void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate)
+{
-    tlb_tag_access_reg_t tag;
     uintptr_t va;
+    index_t index;
     pte_t *t;
-    tag.value = dtlb_tag_access_read();
+    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
-    va = tag.vpn << PAGE_WIDTH;
+    index = tag.vpn % MMU_PAGES_PER_PAGE;
     if (tag.context == ASID_KERNEL) {
         if (!tag.vpn) {
             /* NULL access in kernel */
             do_fast_data_access_mmu_miss_fault(istate, tag,
                 __FUNCTION__);
+        }
         do_fast_data_access_mmu_miss_fault(istate, tag, "Unexpected "
             "kernel page fault.");
+    }
     page_table_lock(AS, true);
     t = page_mapping_find(AS, va);
     if (t) {
         /*
          * The mapping was found in the software page hash table.
          * Insert it into DTLB.
          */
         t->a = true;
-        dtlb_pte_copy(t, true);
+        dtlb_pte_copy(t, index, true);
 #ifdef CONFIG_TSB
-        dtsb_pte_copy(t, true);
+        dtsb_pte_copy(t, index, true);
 #endif
         page_table_unlock(AS, true);
     } else {
         /*
-         * Forward the page fault to the address space page fault handler.
+         * Forward the page fault to the address space page fault
+         * handler.
          */
         page_table_unlock(AS, true);
         if (as_page_fault(va, PF_ACCESS_READ, istate) == AS_PF_FAULT) {
             do_fast_data_access_mmu_miss_fault(istate, tag,
                 __FUNCTION__);
+        }
+    }
+}
-/** DTLB protection fault handler. */
+/** DTLB protection fault handler.
+ *
+ * @param tag Content of the TLB Tag Access register as it existed when the
+ *    trap happened. This is to prevent confusion created by clobbered
+ *    Tag Access register during a nested DTLB miss.
+ * @param istate Interrupted state saved on the stack.
+ */
-void fast_data_access_protection(int n, istate_t *istate)
+void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate)
+{
-    tlb_tag_access_reg_t tag;
     uintptr_t va;
+    index_t index;
     pte_t *t;
-    tag.value = dtlb_tag_access_read();
+    va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE);
-    va = tag.vpn << PAGE_WIDTH;
+    index = tag.vpn % MMU_PAGES_PER_PAGE;   /* 16K-page emulation */
     page_table_lock(AS, true);
     t = page_mapping_find(AS, va);
     if (t && PTE_WRITABLE(t)) {
         /*
          * writable. Demap the old mapping and insert an updated mapping
          * into DTLB.
          */
         t->a = true;
         t->d = true;
-        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY, va);
+        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_SECONDARY,
+            va + index * MMU_PAGE_SIZE);
-        dtlb_pte_copy(t, false);
+        dtlb_pte_copy(t, index, false);
 #ifdef CONFIG_TSB
-        dtsb_pte_copy(t, false);
+        dtsb_pte_copy(t, index, false);
 #endif
         page_table_unlock(AS, true);
     } else {
         /*
          * Forward the page fault to the address space page fault
          * handler.
          */
         page_table_unlock(AS, true);
         if (as_page_fault(va, PF_ACCESS_WRITE, istate) == AS_PF_FAULT) {
             do_fast_data_access_protection_fault(istate, tag,
                 __FUNCTION__);
+        }
+    }
+}
 /** Print contents of both TLBs. */
     for (i = 0; i < ITLB_ENTRY_COUNT; i++) {
         d.value = itlb_data_access_read(i);
         t.value = itlb_tag_read_read(i);
         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
             "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
             "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
             t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
             d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
+    }
     printf("D-TLB contents:\n");
     for (i = 0; i < DTLB_ENTRY_COUNT; i++) {
         d.value = dtlb_data_access_read(i);
         t.value = dtlb_tag_read_read(i);
         printf("%d: vpn=%#llx, context=%d, v=%d, size=%d, nfo=%d, "
             "ie=%d, soft2=%#x, diag=%#x, pfn=%#x, soft=%#x, l=%d, "
             "cp=%d, cv=%d, e=%d, p=%d, w=%d, g=%d\n", i, t.vpn,
             t.context, d.v, d.size, d.nfo, d.ie, d.soft2, d.diag,
             d.pfn, d.soft, d.l, d.cp, d.cv, d.e, d.p, d.w, d.g);
+    }
+}
-void do_fast_instruction_access_mmu_miss_fault(istate_t *istate, const char
+void do_fast_instruction_access_mmu_miss_fault(istate_t *istate,
-    *str)
+    const char *str)
+{
     fault_if_from_uspace(istate, "%s\n", str);
     dump_istate(istate);
     panic("%s\n", str);
+}
-void do_fast_data_access_mmu_miss_fault(istate_t *istate, tlb_tag_access_reg_t
+void do_fast_data_access_mmu_miss_fault(istate_t *istate,
-    tag, const char *str)
+    tlb_tag_access_reg_t tag, const char *str)
+{
     uintptr_t va;
-    va = tag.vpn << PAGE_WIDTH;
+    va = tag.vpn << MMU_PAGE_WIDTH;
+    if (tag.context) {
-    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
+        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
-        tag.context);
+            tag.context);
+    }
     dump_istate(istate);
     printf("Faulting page: %p, ASID=%d\n", va, tag.context);
     panic("%s\n", str);
+}
-void do_fast_data_access_protection_fault(istate_t *istate, tlb_tag_access_reg_t
+void do_fast_data_access_protection_fault(istate_t *istate,
-    tag, const char *str)
+    tlb_tag_access_reg_t tag, const char *str)
+{
     uintptr_t va;
-    va = tag.vpn << PAGE_WIDTH;
+    va = tag.vpn << MMU_PAGE_WIDTH;
+    if (tag.context) {
-    fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
+        fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va,
-        tag.context);
+            tag.context);
+    }
     printf("Faulting page: %p, ASID=%d\n", va, tag.context);
     dump_istate(istate);
     panic("%s\n", str);
+}
     sfsr.value = dtlb_sfsr_read();
     sfar = dtlb_sfar_read();
     printf("DTLB SFSR: asi=%#x, ft=%#x, e=%d, ct=%d, pr=%d, w=%d, ow=%d, "
         "fv=%d\n", sfsr.asi, sfsr.ft, sfsr.e, sfsr.ct, sfsr.pr, sfsr.w,
         sfsr.ow, sfsr.fv);
     printf("DTLB SFAR: address=%p\n", sfar);
     dtlb_sfsr_write(0);
+}
     ctx.v = pc_save.v = mmu_primary_context_read();
     ctx.context = asid;
     mmu_primary_context_write(ctx.v);
-    for (i = 0; i < cnt; i++) {
+    for (i = 0; i < cnt * MMU_PAGES_PER_PAGE; i++) {
-        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i *
+        itlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
-            PAGE_SIZE);
+            page + i * MMU_PAGE_SIZE);
-        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY, page + i *
+        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_PRIMARY,
-            PAGE_SIZE);
+            page + i * MMU_PAGE_SIZE);
+    }
     mmu_primary_context_write(pc_save.v);
     nucleus_leave();

Subversion Repositories HelenOS

(root)/branches/fs/kernel/arch/sparc64/src/mm/tlb.c – Rev 2131 → 2422