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Line 40... Line 40...
40
#include <config.h>
40
#include <config.h>
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41
 
42
#ifdef CONFIG_TSB
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#ifdef CONFIG_TSB
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#include <arch/mm/tsb.h>
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#include <arch/mm/tsb.h>
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#include <arch/memstr.h>
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#include <arch/memstr.h>
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#include <synch/mutex.h>
-
 
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <mm/frame.h>
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#include <mm/frame.h>
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#include <bitops.h>
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#include <bitops.h>
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#include <macros.h>
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#include <macros.h>
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#endif /* CONFIG_TSB */
49
#endif /* CONFIG_TSB */
Line 59... Line 58...
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}
58
}
60
 
59
 
61
int as_constructor_arch(as_t *as, int flags)
60
int as_constructor_arch(as_t *as, int flags)
62
{
61
{
63
#ifdef CONFIG_TSB
62
#ifdef CONFIG_TSB
-
 
63
    /*
-
 
64
     * The order must be calculated with respect to the emulated
-
 
65
     * 16K page size.
-
 
66
     */
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    int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
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    int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
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        sizeof(tsb_entry_t)) >> FRAME_WIDTH);
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        sizeof(tsb_entry_t)) >> FRAME_WIDTH);
-
 
69
 
66
    uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
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    uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
67
 
71
 
68
    if (!tsb)
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    if (!tsb)
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        return -1;
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        return -1;
70
 
74
 
71
    as->arch.itsb = (tsb_entry_t *) tsb;
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    as->arch.itsb = (tsb_entry_t *) tsb;
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    as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
76
    as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
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        sizeof(tsb_entry_t));
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        sizeof(tsb_entry_t));
-
 
78
 
74
    memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT)
79
    memsetb((uintptr_t) as->arch.itsb,
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        * sizeof(tsb_entry_t), 0);
80
        (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
76
#endif
81
#endif
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    return 0;
82
    return 0;
78
}
83
}
79
 
84
 
80
int as_destructor_arch(as_t *as)
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int as_destructor_arch(as_t *as)
81
{
86
{
82
#ifdef CONFIG_TSB
87
#ifdef CONFIG_TSB
-
 
88
    /*
-
 
89
     * The count must be calculated with respect to the emualted 16K page
-
 
90
     * size.
-
 
91
     */
83
    count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
92
    count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
84
        sizeof(tsb_entry_t)) >> FRAME_WIDTH;
93
        sizeof(tsb_entry_t)) >> FRAME_WIDTH;
85
    frame_free(KA2PA((uintptr_t) as->arch.itsb));
94
    frame_free(KA2PA((uintptr_t) as->arch.itsb));
86
    return cnt;
95
    return cnt;
87
#else
96
#else
88
    return 0;
97
    return 0;
89
#endif
98
#endif
90
}
99
}
91
 
100
 
92
int as_create_arch(as_t *as, int flags)
101
int as_create_arch(as_t *as, int flags)
93
{
102
{
94
#ifdef CONFIG_TSB
103
#ifdef CONFIG_TSB
95
    ipl_t ipl;
-
 
96
 
-
 
97
    ipl = interrupts_disable();
-
 
98
    mutex_lock_active(&as->lock);   /* completely unnecessary, but polite */
-
 
99
    tsb_invalidate(as, 0, (count_t) -1);
104
    tsb_invalidate(as, 0, (count_t) -1);
100
    mutex_unlock(&as->lock);
-
 
101
    interrupts_restore(ipl);
-
 
102
#endif
105
#endif
103
    return 0;
106
    return 0;
104
}
107
}
105
 
108
 
106
/** Perform sparc64-specific tasks when an address space becomes active on the
109
/** Perform sparc64-specific tasks when an address space becomes active on the
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void as_install_arch(as_t *as)
116
void as_install_arch(as_t *as)
114
{
117
{
115
    tlb_context_reg_t ctx;
118
    tlb_context_reg_t ctx;
116
   
119
   
117
    /*
120
    /*
118
     * Note that we don't lock the address space.
121
     * Note that we don't and may not lock the address space. That's ok
119
     * That's correct - we can afford it here
-
 
120
     * because we only read members that are
122
     * since we only read members that are currently read-only.
-
 
123
     *
121
     * currently read-only.
124
     * Moreover, the as->asid is protected by asidlock, which is being held.
122
     */
125
     */
123
   
126
   
124
    /*
127
    /*
125
     * Write ASID to secondary context register.
128
     * Write ASID to secondary context register. The primary context
126
     * The primary context register has to be set
-
 
127
     * from TL>0 so it will be filled from the
129
     * register has to be set from TL>0 so it will be filled from the
128
     * secondary context register from the TL=1
130
     * secondary context register from the TL=1 code just before switch to
129
     * code just before switch to userspace.
131
     * userspace.
130
     */
132
     */
131
    ctx.v = 0;
133
    ctx.v = 0;
132
    ctx.context = as->asid;
134
    ctx.context = as->asid;
133
    mmu_secondary_context_write(ctx.v);
135
    mmu_secondary_context_write(ctx.v);
134
 
136
 
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137
 
139
 
138
    ASSERT(as->arch.itsb && as->arch.dtsb);
140
    ASSERT(as->arch.itsb && as->arch.dtsb);
139
 
141
 
140
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
142
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
141
       
143
       
142
    if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
144
    if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
143
        /*
145
        /*
144
         * TSBs were allocated from memory not covered
146
         * TSBs were allocated from memory not covered
145
         * by the locked 4M kernel DTLB entry. We need
147
         * by the locked 4M kernel DTLB entry. We need
146
         * to map both TSBs explicitly.
148
         * to map both TSBs explicitly.
147
         */
149
         */
Line 156... Line 158...
156
       
158
       
157
    tsb_base.value = 0;
159
    tsb_base.value = 0;
158
    tsb_base.size = TSB_SIZE;
160
    tsb_base.size = TSB_SIZE;
159
    tsb_base.split = 0;
161
    tsb_base.split = 0;
160
 
162
 
161
    tsb_base.base = ((uintptr_t) as->arch.itsb) >> PAGE_WIDTH;
163
    tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
162
    itsb_base_write(tsb_base.value);
164
    itsb_base_write(tsb_base.value);
163
    tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH;
165
    tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
164
    dtsb_base_write(tsb_base.value);
166
    dtsb_base_write(tsb_base.value);
165
#endif
167
#endif
166
}
168
}
167
 
169
 
168
/** Perform sparc64-specific tasks when an address space is removed from the
170
/** Perform sparc64-specific tasks when an address space is removed from the
Line 174... Line 176...
174
 */
176
 */
175
void as_deinstall_arch(as_t *as)
177
void as_deinstall_arch(as_t *as)
176
{
178
{
177
 
179
 
178
    /*
180
    /*
179
     * Note that we don't lock the address space.
181
     * Note that we don't and may not lock the address space. That's ok
180
     * That's correct - we can afford it here
-
 
181
     * because we only read members that are
182
     * since we only read members that are currently read-only.
-
 
183
     *
182
     * currently read-only.
184
     * Moreover, the as->asid is protected by asidlock, which is being held.
183
     */
185
     */
184
 
186
 
185
#ifdef CONFIG_TSB
187
#ifdef CONFIG_TSB
186
    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
188
    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
187
 
189
 
188
    ASSERT(as->arch.itsb && as->arch.dtsb);
190
    ASSERT(as->arch.itsb && as->arch.dtsb);
189
 
191
 
190
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
192
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
191
       
193
       
192
    if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
194
    if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
193
        /*
195
        /*
194
         * TSBs were allocated from memory not covered
196
         * TSBs were allocated from memory not covered
195
         * by the locked 4M kernel DTLB entry. We need
197
         * by the locked 4M kernel DTLB entry. We need
196
         * to demap the entry installed by as_install_arch().
198
         * to demap the entry installed by as_install_arch().
197
         */
199
         */