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Rev 2927 Rev 3674
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#include <arch/drivers/z8530.h>
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#include <arch/drivers/z8530.h>
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#include <ddi/irq.h>
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#include <ddi/irq.h>
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#include <ipc/irq.h>
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#include <ipc/irq.h>
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#include <arch/interrupt.h>
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#include <arch/interrupt.h>
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#include <arch/drivers/kbd.h>
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#include <arch/drivers/kbd.h>
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#include <arch/drivers/fhc.h>
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#include <cpu.h>
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#include <cpu.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <arch.h>
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#include <arch.h>
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#include <console/chardev.h>
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#include <console/chardev.h>
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#include <console/console.h>
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#include <console/console.h>
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     * Clear any pending TX interrupts or we never manage
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     * Clear any pending TX interrupts or we never manage
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     * to set FHC UART interrupt state to idle.
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     * to set FHC UART interrupt state to idle.
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     */
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     */
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    z8530_write_a(&z8530, WR0, WR0_TX_IP_RST);
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    z8530_write_a(&z8530, WR0, WR0_TX_IP_RST);
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    /* interrupt on all characters */
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    z8530_write_a(&z8530, WR1, WR1_IARCSC);     /* interrupt on all characters */
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    z8530_write_a(&z8530, WR1, WR1_IARCSC);
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    /* 8 bits per character and enable receiver */
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    /* 8 bits per character and enable receiver */
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    z8530_write_a(&z8530, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);
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    z8530_write_a(&z8530, WR3, WR3_RX8BITSCH | WR3_RX_ENABLE);
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    /* Master Interrupt Enable. */
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    z8530_write_a(&z8530, WR9, WR9_MIE);        /* Master Interrupt Enable. */
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    z8530_write_a(&z8530, WR9, WR9_MIE);
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    spinlock_lock(&z8530_irq.lock);
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    spinlock_lock(&z8530_irq.lock);
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    z8530_irq.notif_cfg.notify = false;
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    z8530_irq.notif_cfg.notify = false;
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    spinlock_unlock(&z8530_irq.lock);
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    spinlock_unlock(&z8530_irq.lock);
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    interrupts_restore(ipl);
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    interrupts_restore(ipl);
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    spinlock_unlock(&z8530_irq.lock);
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    spinlock_unlock(&z8530_irq.lock);
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    interrupts_restore(ipl);
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    interrupts_restore(ipl);
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}
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}
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/** Initialize z8530. */
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/** Initialize z8530. */
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void
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void z8530_init(devno_t devno, inr_t inr, uintptr_t vaddr)
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z8530_init(devno_t devno, uintptr_t vaddr, inr_t inr, cir_t cir, void *cir_arg)
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{
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{
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    chardev_initialize("z8530_kbd", &kbrd, &ops);
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    chardev_initialize("z8530_kbd", &kbrd, &ops);
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    stdin = &kbrd;
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    stdin = &kbrd;
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    z8530.devno = devno;
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    z8530.devno = devno;
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    irq_initialize(&z8530_irq);
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    irq_initialize(&z8530_irq);
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    z8530_irq.devno = devno;
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    z8530_irq.devno = devno;
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    z8530_irq.inr = inr;
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    z8530_irq.inr = inr;
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    z8530_irq.claim = z8530_claim;
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    z8530_irq.claim = z8530_claim;
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    z8530_irq.handler = z8530_irq_handler;
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    z8530_irq.handler = z8530_irq_handler;
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    z8530_irq.cir = cir;
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    z8530_irq.cir_arg = cir_arg;
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    irq_register(&z8530_irq);
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    irq_register(&z8530_irq);
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    sysinfo_set_item_val("kbd", NULL, true);
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    sysinfo_set_item_val("kbd", NULL, true);
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    sysinfo_set_item_val("kbd.type", NULL, KBD_Z8530);
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    sysinfo_set_item_val("kbd.type", NULL, KBD_Z8530);
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    sysinfo_set_item_val("kbd.devno", NULL, devno);
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    sysinfo_set_item_val("kbd.devno", NULL, devno);
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    return (z8530_read_a(&z8530, RR0) & RR0_RCA);
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    return (z8530_read_a(&z8530, RR0) & RR0_RCA);
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}
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}
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void z8530_irq_handler(irq_t *irq, void *arg, ...)
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void z8530_irq_handler(irq_t *irq, void *arg, ...)
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{
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{
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    /*
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     * So far, we know we got this interrupt through the FHC.
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     * Since we don't have enough documentation about the FHC
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     * and because the interrupt looks like level sensitive,
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     * we cannot handle it by scheduling one of the level
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     * interrupt traps. Process the interrupt directly.
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     */
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    if (irq->notif_cfg.notify && irq->notif_cfg.answerbox)
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    if (irq->notif_cfg.notify && irq->notif_cfg.answerbox)
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        ipc_irq_send_notif(irq);
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        ipc_irq_send_notif(irq);
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    else
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    else
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        z8530_interrupt();
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        z8530_interrupt();
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    fhc_clear_interrupt(central_fhc, irq->inr);
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}
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}
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/** @}
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/** @}
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 */
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 */