WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/sparc64/src/mm/as.c


/*
 * Copyright (c) 2006 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm
 * @{
 */
/** @file
 */
 
#include <arch/mm/as.h>
#include <arch/mm/tlb.h>
#include <genarch/mm/page_ht.h>
#include <genarch/mm/asid_fifo.h>
#include <debug.h>
#include <config.h>
 
#ifdef CONFIG_TSB
#include <arch/mm/tsb.h>
#include <arch/memstr.h>
#include <arch/asm.h>
#include <mm/frame.h>
#include <bitops.h>
#include <macros.h>
#endif /* CONFIG_TSB */
 
/** Architecture dependent address space init. */
void as_arch_init(void)
{
    if (config.cpu_active == 1) {
        as_operations = &as_ht_operations;
        asid_fifo_init();
    }
}
 
int as_constructor_arch(as_t *as, int flags)
{
#ifdef CONFIG_TSB
    /*
     * The order must be calculated with respect to the emulated
     * 16K page size.
     */
    int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
        sizeof(tsb_entry_t)) >> FRAME_WIDTH);
 
    uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA);
 
    if (!tsb)
        return -1;
 
    as->arch.itsb = (tsb_entry_t *) tsb;
    as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT *
        sizeof(tsb_entry_t));
 
    memsetb(as->arch.itsb,
        (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
#endif
    return 0;
}
 
int as_destructor_arch(as_t *as)
{
#ifdef CONFIG_TSB
    /*
     * The count must be calculated with respect to the emualted 16K page
     * size.
     */
    count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
        sizeof(tsb_entry_t)) >> FRAME_WIDTH;
    frame_free(KA2PA((uintptr_t) as->arch.itsb));
    return cnt;
#else
    return 0;
#endif
}
 
int as_create_arch(as_t *as, int flags)
{
#ifdef CONFIG_TSB
    tsb_invalidate(as, 0, (count_t) -1);
#endif
    return 0;
}
 
/** Perform sparc64-specific tasks when an address space becomes active on the
 * processor.
 *
 * Install ASID and map TSBs.
 *
 * @param as Address space.
 */
void as_install_arch(as_t *as)
{
    tlb_context_reg_t ctx;
   
    /*
     * Note that we don't and may not lock the address space. That's ok
     * since we only read members that are currently read-only.
     *
     * Moreover, the as->asid is protected by asidlock, which is being held.
     */
   
    /*
     * Write ASID to secondary context register. The primary context
     * register has to be set from TL>0 so it will be filled from the
     * secondary context register from the TL=1 code just before switch to
     * userspace.
     */
    ctx.v = 0;
    ctx.context = as->asid;
    mmu_secondary_context_write(ctx.v);
 
#ifdef CONFIG_TSB   
    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
 
    ASSERT(as->arch.itsb && as->arch.dtsb);
 
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
       
    if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
        /*
         * TSBs were allocated from memory not covered
         * by the locked 4M kernel DTLB entry. We need
         * to map both TSBs explicitly.
         */
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
        dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
    }
       
    /*
     * Setup TSB Base registers.
     */
    tsb_base_reg_t tsb_base;
       
    tsb_base.value = 0;
    tsb_base.size = TSB_SIZE;
    tsb_base.split = 0;
 
    tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
    itsb_base_write(tsb_base.value);
    tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
    dtsb_base_write(tsb_base.value);
   
#if defined (US3)
    /*
     * Clear the extension registers.
     * In HelenOS, primary and secondary context registers contain
     * equal values and kernel misses (context 0, ie. the nucleus context)
     * are excluded from the TSB miss handler, so it makes no sense
     * to have separate TSBs for primary, secondary and nucleus contexts.
     * Clearing the extension registers will ensure that the value of the
     * TSB Base register will be used as an address of TSB, making the code
     * compatible with the US port.
     */
    itsb_primary_extension_write(0);
    itsb_nucleus_extension_write(0);
    dtsb_primary_extension_write(0);
    dtsb_secondary_extension_write(0);
    dtsb_nucleus_extension_write(0);
#endif
#endif
}
 
/** Perform sparc64-specific tasks when an address space is removed from the
 * processor.
 *
 * Demap TSBs.
 *
 * @param as Address space.
 */
void as_deinstall_arch(as_t *as)
{
 
    /*
     * Note that we don't and may not lock the address space. That's ok
     * since we only read members that are currently read-only.
     *
     * Moreover, the as->asid is protected by asidlock, which is being held.
     */
 
#ifdef CONFIG_TSB
    uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
 
    ASSERT(as->arch.itsb && as->arch.dtsb);
 
    uintptr_t tsb = (uintptr_t) as->arch.itsb;
       
    if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
        /*
         * TSBs were allocated from memory not covered
         * by the locked 4M kernel DTLB entry. We need
         * to demap the entry installed by as_install_arch().
         */
        dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
    }
#endif
}
 
/** @}
 */
 

Rev 3153	Rev 3674
1	/*	1	/*
2	* Copyright (c) 2006 Jakub Jermar	2	* Copyright (c) 2006 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch/mm/as.h>	35	#include <arch/mm/as.h>
36	#include <arch/mm/tlb.h>	36	#include <arch/mm/tlb.h>
37	#include <genarch/mm/page_ht.h>	37	#include <genarch/mm/page_ht.h>
38	#include <genarch/mm/asid_fifo.h>	38	#include <genarch/mm/asid_fifo.h>
39	#include <debug.h>	39	#include <debug.h>
40	#include <config.h>	40	#include <config.h>
41		41
42	#ifdef CONFIG_TSB	42	#ifdef CONFIG_TSB
43	#include <arch/mm/tsb.h>	43	#include <arch/mm/tsb.h>
44	#include <arch/memstr.h>	44	#include <arch/memstr.h>
45	#include <arch/asm.h>	45	#include <arch/asm.h>
46	#include <mm/frame.h>	46	#include <mm/frame.h>
47	#include <bitops.h>	47	#include <bitops.h>
48	#include <macros.h>	48	#include <macros.h>
49	#endif /* CONFIG_TSB */	49	#endif /* CONFIG_TSB */
50		50
51	/** Architecture dependent address space init. */	51	/** Architecture dependent address space init. */
52	void as_arch_init(void)	52	void as_arch_init(void)
53	{	53	{
54	if (config.cpu_active == 1) {	54	if (config.cpu_active == 1) {
55	as_operations = &as_ht_operations;	55	as_operations = &as_ht_operations;
56	asid_fifo_init();	56	asid_fifo_init();
57	}	57	}
58	}	58	}
59		59
60	int as_constructor_arch(as_t *as, int flags)	60	int as_constructor_arch(as_t *as, int flags)
61	{	61	{
62	#ifdef CONFIG_TSB	62	#ifdef CONFIG_TSB
63	/*	63	/*
64	* The order must be calculated with respect to the emulated	64	* The order must be calculated with respect to the emulated
65	* 16K page size.	65	* 16K page size.
66	*/	66	*/
67	int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *	67	int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
68	sizeof(tsb_entry_t)) >> FRAME_WIDTH);	68	sizeof(tsb_entry_t)) >> FRAME_WIDTH);
69		69
70	uintptr_t tsb = (uintptr_t) frame_alloc(order, flags \| FRAME_KA);	70	uintptr_t tsb = (uintptr_t) frame_alloc(order, flags \| FRAME_KA);
71		71
72	if (!tsb)	72	if (!tsb)
73	return -1;	73	return -1;
74		74
75	as->arch.itsb = (tsb_entry_t *) tsb;	75	as->arch.itsb = (tsb_entry_t *) tsb;
76	as->arch.dtsb = (tsb_entry_t ) (tsb + ITSB_ENTRY_COUNT	76	as->arch.dtsb = (tsb_entry_t ) (tsb + ITSB_ENTRY_COUNT
77	sizeof(tsb_entry_t));	77	sizeof(tsb_entry_t));
78		78
79	memsetb(as->arch.itsb,	79	memsetb(as->arch.itsb,
80	(ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);	80	(ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * sizeof(tsb_entry_t), 0);
81	#endif	81	#endif
82	return 0;	82	return 0;
83	}	83	}
84		84
85	int as_destructor_arch(as_t *as)	85	int as_destructor_arch(as_t *as)
86	{	86	{
87	#ifdef CONFIG_TSB	87	#ifdef CONFIG_TSB
88	/*	88	/*
89	* The count must be calculated with respect to the emualted 16K page	89	* The count must be calculated with respect to the emualted 16K page
90	* size.	90	* size.
91	*/	91	*/
92	count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *	92	count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) *
93	sizeof(tsb_entry_t)) >> FRAME_WIDTH;	93	sizeof(tsb_entry_t)) >> FRAME_WIDTH;
94	frame_free(KA2PA((uintptr_t) as->arch.itsb));	94	frame_free(KA2PA((uintptr_t) as->arch.itsb));
95	return cnt;	95	return cnt;
96	#else	96	#else
97	return 0;	97	return 0;
98	#endif	98	#endif
99	}	99	}
100		100
101	int as_create_arch(as_t *as, int flags)	101	int as_create_arch(as_t *as, int flags)
102	{	102	{
103	#ifdef CONFIG_TSB	103	#ifdef CONFIG_TSB
104	tsb_invalidate(as, 0, (count_t) -1);	104	tsb_invalidate(as, 0, (count_t) -1);
105	#endif	105	#endif
106	return 0;	106	return 0;
107	}	107	}
108		108
109	/** Perform sparc64-specific tasks when an address space becomes active on the	109	/** Perform sparc64-specific tasks when an address space becomes active on the
110	* processor.	110	* processor.
111	*	111	*
112	* Install ASID and map TSBs.	112	* Install ASID and map TSBs.
113	*	113	*
114	* @param as Address space.	114	* @param as Address space.
115	*/	115	*/
116	void as_install_arch(as_t *as)	116	void as_install_arch(as_t *as)
117	{	117	{
118	tlb_context_reg_t ctx;	118	tlb_context_reg_t ctx;
119		119
120	/*	120	/*
121	* Note that we don't and may not lock the address space. That's ok	121	* Note that we don't and may not lock the address space. That's ok
122	* since we only read members that are currently read-only.	122	* since we only read members that are currently read-only.
123	*	123	*
124	* Moreover, the as->asid is protected by asidlock, which is being held.	124	* Moreover, the as->asid is protected by asidlock, which is being held.
125	*/	125	*/
126		126
127	/*	127	/*
128	* Write ASID to secondary context register. The primary context	128	* Write ASID to secondary context register. The primary context
129	* register has to be set from TL>0 so it will be filled from the	129	* register has to be set from TL>0 so it will be filled from the
130	* secondary context register from the TL=1 code just before switch to	130	* secondary context register from the TL=1 code just before switch to
131	* userspace.	131	* userspace.
132	*/	132	*/
133	ctx.v = 0;	133	ctx.v = 0;
134	ctx.context = as->asid;	134	ctx.context = as->asid;
135	mmu_secondary_context_write(ctx.v);	135	mmu_secondary_context_write(ctx.v);
136		136
137	#ifdef CONFIG_TSB	137	#ifdef CONFIG_TSB
138	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);	138	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
139		139
140	ASSERT(as->arch.itsb && as->arch.dtsb);	140	ASSERT(as->arch.itsb && as->arch.dtsb);
141		141
142	uintptr_t tsb = (uintptr_t) as->arch.itsb;	142	uintptr_t tsb = (uintptr_t) as->arch.itsb;
143		143
144	if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {	144	if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
145	/*	145	/*
146	* TSBs were allocated from memory not covered	146	* TSBs were allocated from memory not covered
147	* by the locked 4M kernel DTLB entry. We need	147	* by the locked 4M kernel DTLB entry. We need
148	* to map both TSBs explicitly.	148	* to map both TSBs explicitly.
149	*/	149	*/
150	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);	150	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
151	dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);	151	dtlb_insert_mapping(tsb, KA2PA(tsb), PAGESIZE_64K, true, true);
152	}	152	}
153		153
154	/*	154	/*
155	* Setup TSB Base registers.	155	* Setup TSB Base registers.
156	*/	156	*/
157	tsb_base_reg_t tsb_base;	157	tsb_base_reg_t tsb_base;
158		158
159	tsb_base.value = 0;	159	tsb_base.value = 0;
160	tsb_base.size = TSB_SIZE;	160	tsb_base.size = TSB_SIZE;
161	tsb_base.split = 0;	161	tsb_base.split = 0;
162		162
163	tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;	163	tsb_base.base = ((uintptr_t) as->arch.itsb) >> MMU_PAGE_WIDTH;
164	itsb_base_write(tsb_base.value);	164	itsb_base_write(tsb_base.value);
165	tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;	165	tsb_base.base = ((uintptr_t) as->arch.dtsb) >> MMU_PAGE_WIDTH;
166	dtsb_base_write(tsb_base.value);	166	dtsb_base_write(tsb_base.value);
-		167
-		168	#if defined (US3)
-		169	/*
-		170	* Clear the extension registers.
-		171	* In HelenOS, primary and secondary context registers contain
-		172	* equal values and kernel misses (context 0, ie. the nucleus context)
-		173	* are excluded from the TSB miss handler, so it makes no sense
-		174	* to have separate TSBs for primary, secondary and nucleus contexts.
-		175	* Clearing the extension registers will ensure that the value of the
-		176	* TSB Base register will be used as an address of TSB, making the code
-		177	* compatible with the US port.
-		178	*/
-		179	itsb_primary_extension_write(0);
-		180	itsb_nucleus_extension_write(0);
-		181	dtsb_primary_extension_write(0);
-		182	dtsb_secondary_extension_write(0);
-		183	dtsb_nucleus_extension_write(0);
-		184	#endif
167	#endif	185	#endif
168	}	186	}
169		187
170	/** Perform sparc64-specific tasks when an address space is removed from the	188	/** Perform sparc64-specific tasks when an address space is removed from the
171	* processor.	189	* processor.
172	*	190	*
173	* Demap TSBs.	191	* Demap TSBs.
174	*	192	*
175	* @param as Address space.	193	* @param as Address space.
176	*/	194	*/
177	void as_deinstall_arch(as_t *as)	195	void as_deinstall_arch(as_t *as)
178	{	196	{
179		197
180	/*	198	/*
181	* Note that we don't and may not lock the address space. That's ok	199	* Note that we don't and may not lock the address space. That's ok
182	* since we only read members that are currently read-only.	200	* since we only read members that are currently read-only.
183	*	201	*
184	* Moreover, the as->asid is protected by asidlock, which is being held.	202	* Moreover, the as->asid is protected by asidlock, which is being held.
185	*/	203	*/
186		204
187	#ifdef CONFIG_TSB	205	#ifdef CONFIG_TSB
188	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);	206	uintptr_t base = ALIGN_DOWN(config.base, 1 << KERNEL_PAGE_WIDTH);
189		207
190	ASSERT(as->arch.itsb && as->arch.dtsb);	208	ASSERT(as->arch.itsb && as->arch.dtsb);
191		209
192	uintptr_t tsb = (uintptr_t) as->arch.itsb;	210	uintptr_t tsb = (uintptr_t) as->arch.itsb;
193		211
194	if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {	212	if (!overlaps(tsb, 8 * MMU_PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) {
195	/*	213	/*
196	* TSBs were allocated from memory not covered	214	* TSBs were allocated from memory not covered
197	* by the locked 4M kernel DTLB entry. We need	215	* by the locked 4M kernel DTLB entry. We need
198	* to demap the entry installed by as_install_arch().	216	* to demap the entry installed by as_install_arch().
199	*/	217	*/
200	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);	218	dtlb_demap(TLB_DEMAP_PAGE, TLB_DEMAP_NUCLEUS, tsb);
201	}	219	}
202	#endif	220	#endif
203	}	221	}
204		222
205	/** @}	223	/** @}
206	*/	224	*/
207		225

Subversion Repositories HelenOS

(root)/branches/dynload/kernel/arch/sparc64/src/mm/as.c – Rev 3153 → 3674