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1
/*
1
/*
2
 * Copyright (c) 2006 Jakub Jermar
2
 * Copyright (c) 2006 Jakub Jermar
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 * All rights reserved.
3
 * All rights reserved.
4
 *
4
 *
5
 * Redistribution and use in source and binary forms, with or without
5
 * Redistribution and use in source and binary forms, with or without
6
 * modification, are permitted provided that the following conditions
6
 * modification, are permitted provided that the following conditions
7
 * are met:
7
 * are met:
8
 *
8
 *
9
 * - Redistributions of source code must retain the above copyright
9
 * - Redistributions of source code must retain the above copyright
10
 *   notice, this list of conditions and the following disclaimer.
10
 *   notice, this list of conditions and the following disclaimer.
11
 * - Redistributions in binary form must reproduce the above copyright
11
 * - Redistributions in binary form must reproduce the above copyright
12
 *   notice, this list of conditions and the following disclaimer in the
12
 *   notice, this list of conditions and the following disclaimer in the
13
 *   documentation and/or other materials provided with the distribution.
13
 *   documentation and/or other materials provided with the distribution.
14
 * - The name of the author may not be used to endorse or promote products
14
 * - The name of the author may not be used to endorse or promote products
15
 *   derived from this software without specific prior written permission.
15
 *   derived from this software without specific prior written permission.
16
 *
16
 *
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
17
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
18
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
19
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
20
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
21
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
25
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27
 */
27
 */
28
 
28
 
29
/** @addtogroup sparc64
29
/** @addtogroup sparc64
30
 * @{
30
 * @{
31
 */
31
 */
32
/**
32
/**
33
 * @file
33
 * @file
34
 * @brief   PCI driver.
34
 * @brief   PCI driver.
35
 */
35
 */
36
 
36
 
37
#include <arch/drivers/pci.h>
37
#include <arch/drivers/pci.h>
38
#include <genarch/ofw/ofw_tree.h>
38
#include <genarch/ofw/ofw_tree.h>
39
#include <arch/trap/interrupt.h>
39
#include <arch/trap/interrupt.h>
40
#include <mm/page.h>
40
#include <mm/page.h>
41
#include <mm/slab.h>
41
#include <mm/slab.h>
42
#include <arch/types.h>
42
#include <arch/types.h>
43
#include <debug.h>
43
#include <debug.h>
44
#include <print.h>
44
#include <print.h>
45
#include <func.h>
45
#include <func.h>
46
#include <arch/asm.h>
46
#include <arch/asm.h>
47
 
47
 
48
#define PCI_SABRE_REGS_REG  0
48
#define SABRE_INTERNAL_REG  0
-
 
49
#define PSYCHO_INTERNAL_REG 2   
49
 
50
 
50
#define PCI_SABRE_IMAP_BASE 0x200
51
#define OBIO_IMR_BASE   0x200
51
#define PCI_SABRE_ICLR_BASE 0x300
52
#define OBIO_IMR(ino)   (OBIO_IMR_BASE + ((ino) & INO_MASK))
52
 
53
 
53
#define PCI_PSYCHO_REGS_REG 2   
54
#define OBIO_CIR_BASE   0x300
-
 
55
#define OBIO_CIR(ino)   (OBIO_CIR_BASE + ((ino) & INO_MASK))
54
 
56
 
55
#define PCI_PSYCHO_IMAP_BASE    0x200
57
static void obio_enable_interrupt(pci_t *, int);
56
#define PCI_PSYCHO_ICLR_BASE    0x300   
58
static void obio_clear_interrupt(pci_t *, int);
57
 
59
 
58
static pci_t *pci_sabre_init(ofw_tree_node_t *node);
60
static pci_t *pci_sabre_init(ofw_tree_node_t *);
59
static void pci_sabre_enable_interrupt(pci_t *pci, int inr);
-
 
60
static void pci_sabre_clear_interrupt(pci_t *pci, int inr);
-
 
61
 
-
 
62
static pci_t *pci_psycho_init(ofw_tree_node_t *node);
61
static pci_t *pci_psycho_init(ofw_tree_node_t *);
63
static void pci_psycho_enable_interrupt(pci_t *pci, int inr);
-
 
64
static void pci_psycho_clear_interrupt(pci_t *pci, int inr);
-
 
65
 
62
 
66
/** PCI operations for Sabre model. */
63
/** PCI operations for Sabre model. */
67
static pci_operations_t pci_sabre_ops = {
64
static pci_operations_t pci_sabre_ops = {
68
    .enable_interrupt = pci_sabre_enable_interrupt,
65
    .enable_interrupt = obio_enable_interrupt,
69
    .clear_interrupt = pci_sabre_clear_interrupt
66
    .clear_interrupt = obio_clear_interrupt
70
};
67
};
71
/** PCI operations for Psycho model. */
68
/** PCI operations for Psycho model. */
72
static pci_operations_t pci_psycho_ops = {
69
static pci_operations_t pci_psycho_ops = {
73
    .enable_interrupt = pci_psycho_enable_interrupt,
70
    .enable_interrupt = obio_enable_interrupt,
74
    .clear_interrupt = pci_psycho_clear_interrupt
71
    .clear_interrupt = obio_clear_interrupt
75
};
72
};
76
 
73
 
77
/** Initialize PCI controller (model Sabre).
74
/** Initialize PCI controller (model Sabre).
78
 *
75
 *
79
 * @param node OpenFirmware device tree node of the Sabre.
76
 * @param node      OpenFirmware device tree node of the Sabre.
80
 *
77
 *
81
 * @return Address of the initialized PCI structure.
78
 * @return      Address of the initialized PCI structure.
82
 */
79
 */
83
pci_t *pci_sabre_init(ofw_tree_node_t *node)
80
pci_t *pci_sabre_init(ofw_tree_node_t *node)
84
{
81
{
85
    pci_t *pci;
82
    pci_t *pci;
86
    ofw_tree_property_t *prop;
83
    ofw_tree_property_t *prop;
87
 
84
 
88
    /*
85
    /*
89
     * Get registers.
86
     * Get registers.
90
     */
87
     */
91
    prop = ofw_tree_getprop(node, "reg");
88
    prop = ofw_tree_getprop(node, "reg");
92
    if (!prop || !prop->value)
89
    if (!prop || !prop->value)
93
        return NULL;
90
        return NULL;
94
 
91
 
95
    ofw_upa_reg_t *reg = prop->value;
92
    ofw_upa_reg_t *reg = prop->value;
96
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
93
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
97
 
94
 
98
    if (regs < PCI_SABRE_REGS_REG + 1)
95
    if (regs < SABRE_INTERNAL_REG + 1)
99
        return NULL;
96
        return NULL;
100
 
97
 
101
    uintptr_t paddr;
98
    uintptr_t paddr;
102
    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_SABRE_REGS_REG], &paddr))
99
    if (!ofw_upa_apply_ranges(node->parent, &reg[SABRE_INTERNAL_REG],
-
 
100
        &paddr))
103
        return NULL;
101
        return NULL;
104
 
102
 
105
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
103
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
106
    if (!pci)
104
    if (!pci)
107
        return NULL;
105
        return NULL;
108
 
106
 
109
    pci->model = PCI_SABRE;
107
    pci->model = PCI_SABRE;
110
    pci->op = &pci_sabre_ops;
108
    pci->op = &pci_sabre_ops;
111
    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_SABRE_REGS_REG].size);
109
    pci->reg = (uint64_t *) hw_map(paddr, reg[SABRE_INTERNAL_REG].size);
112
 
110
 
113
    return pci;
111
    return pci;
114
}
112
}
115
 
113
 
116
 
114
 
117
/** Initialize the Psycho PCI controller.
115
/** Initialize the Psycho PCI controller.
118
 *
116
 *
119
 * @param node OpenFirmware device tree node of the Psycho.
117
 * @param node      OpenFirmware device tree node of the Psycho.
120
 *
118
 *
121
 * @return Address of the initialized PCI structure.
119
 * @return      Address of the initialized PCI structure.
122
 */
120
 */
123
pci_t *pci_psycho_init(ofw_tree_node_t *node)
121
pci_t *pci_psycho_init(ofw_tree_node_t *node)
124
{
122
{
125
    pci_t *pci;
123
    pci_t *pci;
126
    ofw_tree_property_t *prop;
124
    ofw_tree_property_t *prop;
127
 
125
 
128
    /*
126
    /*
129
     * Get registers.
127
     * Get registers.
130
     */
128
     */
131
    prop = ofw_tree_getprop(node, "reg");
129
    prop = ofw_tree_getprop(node, "reg");
132
    if (!prop || !prop->value)
130
    if (!prop || !prop->value)
133
        return NULL;
131
        return NULL;
134
 
132
 
135
    ofw_upa_reg_t *reg = prop->value;
133
    ofw_upa_reg_t *reg = prop->value;
136
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
134
    count_t regs = prop->size / sizeof(ofw_upa_reg_t);
137
 
135
 
138
    if (regs < PCI_PSYCHO_REGS_REG + 1)
136
    if (regs < PSYCHO_INTERNAL_REG + 1)
139
        return NULL;
137
        return NULL;
140
 
138
 
141
    uintptr_t paddr;
139
    uintptr_t paddr;
142
    if (!ofw_upa_apply_ranges(node->parent, &reg[PCI_PSYCHO_REGS_REG], &paddr))
140
    if (!ofw_upa_apply_ranges(node->parent, &reg[PSYCHO_INTERNAL_REG],
-
 
141
        &paddr))
143
        return NULL;
142
        return NULL;
144
 
143
 
145
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
144
    pci = (pci_t *) malloc(sizeof(pci_t), FRAME_ATOMIC);
146
    if (!pci)
145
    if (!pci)
147
        return NULL;
146
        return NULL;
148
 
147
 
149
    pci->model = PCI_PSYCHO;
148
    pci->model = PCI_PSYCHO;
150
    pci->op = &pci_psycho_ops;
149
    pci->op = &pci_psycho_ops;
151
    pci->reg = (uint64_t *) hw_map(paddr, reg[PCI_PSYCHO_REGS_REG].size);
150
    pci->reg = (uint64_t *) hw_map(paddr, reg[PSYCHO_INTERNAL_REG].size);
152
 
151
 
153
    return pci;
152
    return pci;
154
}
153
}
155
 
154
 
156
void pci_sabre_enable_interrupt(pci_t *pci, int inr)
155
void obio_enable_interrupt(pci_t *pci, int inr)
157
{
-
 
158
    pci->reg[PCI_SABRE_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
-
 
159
}
-
 
160
 
-
 
161
void pci_sabre_clear_interrupt(pci_t *pci, int inr)
-
 
162
{
156
{
163
    pci->reg[PCI_SABRE_ICLR_BASE + (inr & INO_MASK)] = 0;
157
    pci->reg[OBIO_IMR(inr & INO_MASK)] |= IMAP_V_MASK;
164
}
158
}
165
 
159
 
166
void pci_psycho_enable_interrupt(pci_t *pci, int inr)
160
void obio_clear_interrupt(pci_t *pci, int inr)
167
{
161
{
168
    pci->reg[PCI_PSYCHO_IMAP_BASE + (inr & INO_MASK)] |= IMAP_V_MASK;
-
 
169
}
-
 
170
 
-
 
171
void pci_psycho_clear_interrupt(pci_t *pci, int inr)
-
 
172
{
-
 
173
    pci->reg[PCI_PSYCHO_ICLR_BASE + (inr & INO_MASK)] = 0;
162
    pci->reg[OBIO_CIR(inr & INO_MASK)] = 0; /* set IDLE */
174
}
163
}
175
 
164
 
176
/** Initialize PCI controller. */
165
/** Initialize PCI controller. */
177
pci_t *pci_init(ofw_tree_node_t *node)
166
pci_t *pci_init(ofw_tree_node_t *node)
178
{
167
{
179
    ofw_tree_property_t *prop;
168
    ofw_tree_property_t *prop;
180
 
169
 
181
    /*
170
    /*
182
     * First, verify this is a PCI node.
171
     * First, verify this is a PCI node.
183
     */
172
     */
184
    ASSERT(strcmp(ofw_tree_node_name(node), "pci") == 0);
173
    ASSERT(strcmp(ofw_tree_node_name(node), "pci") == 0);
185
 
174
 
186
    /*
175
    /*
187
     * Determine PCI controller model.
176
     * Determine PCI controller model.
188
     */
177
     */
189
    prop = ofw_tree_getprop(node, "model");
178
    prop = ofw_tree_getprop(node, "model");
190
    if (!prop || !prop->value)
179
    if (!prop || !prop->value)
191
        return NULL;
180
        return NULL;
192
   
181
   
193
    if (strcmp(prop->value, "SUNW,sabre") == 0) {
182
    if (strcmp(prop->value, "SUNW,sabre") == 0) {
194
        /*
183
        /*
195
         * PCI controller Sabre.
184
         * PCI controller Sabre.
196
         * This model is found on UltraSPARC IIi based machines.
185
         * This model is found on UltraSPARC IIi based machines.
197
         */
186
         */
198
        return pci_sabre_init(node);
187
        return pci_sabre_init(node);
199
    } else if (strcmp(prop->value, "SUNW,psycho") == 0) {
188
    } else if (strcmp(prop->value, "SUNW,psycho") == 0) {
200
        /*
189
        /*
201
         * PCI controller Psycho.
190
         * PCI controller Psycho.
202
         * Used on UltraSPARC II based processors, for instance,
191
         * Used on UltraSPARC II based processors, for instance,
203
         * on Ultra 60.
192
         * on Ultra 60.
204
         */
193
         */
205
        return pci_psycho_init(node);
194
        return pci_psycho_init(node);
206
    } else {
195
    } else {
207
        /*
196
        /*
208
         * Unsupported model.
197
         * Unsupported model.
209
         */
198
         */
210
        printf("Unsupported PCI controller model (%s).\n", prop->value);
199
        printf("Unsupported PCI controller model (%s).\n", prop->value);
211
    }
200
    }
212
 
201
 
213
    return NULL;
202
    return NULL;
214
}
203
}
215
 
204
 
216
void pci_enable_interrupt(pci_t *pci, int inr)
205
void pci_enable_interrupt(pci_t *pci, int inr)
217
{
206
{
218
    ASSERT(pci->model);
-
 
219
    ASSERT(pci->op && pci->op->enable_interrupt);
207
    ASSERT(pci->op && pci->op->enable_interrupt);
220
    pci->op->enable_interrupt(pci, inr);
208
    pci->op->enable_interrupt(pci, inr);
221
}
209
}
222
 
210
 
223
void pci_clear_interrupt(pci_t *pci, int inr)
211
void pci_clear_interrupt(void *pcip, int inr)
224
{
212
{
225
    ASSERT(pci->model);
213
    pci_t *pci = (pci_t *)pcip;
-
 
214
 
226
    ASSERT(pci->op && pci->op->clear_interrupt);
215
    ASSERT(pci->op && pci->op->clear_interrupt);
227
    pci->op->clear_interrupt(pci, inr);
216
    pci->op->clear_interrupt(pci, inr);
228
}
217
}
229
 
218
 
230
/** @}
219
/** @}
231
 */
220
 */
232
 
221