WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/sparc64/include/mm/mmu.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64mm  
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_MMU_H_
#define KERN_sparc64_MMU_H_
 
#if defined(US)
/* LSU Control Register ASI. */
#define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
#endif
 
/* I-MMU ASIs. */
#define ASI_IMMU            0x50
#define ASI_IMMU_TSB_8KB_PTR_REG    0x51    
#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
#define ASI_ITLB_DATA_IN_REG        0x54
#define ASI_ITLB_DATA_ACCESS_REG    0x55
#define ASI_ITLB_TAG_READ_REG       0x56
#define ASI_IMMU_DEMAP          0x57
 
/* Virtual Addresses within ASI_IMMU. */
#define VA_IMMU_TSB_TAG_TARGET      0x0 /**< IMMU TSB tag target register. */
#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
#if defined (US3)
#define VA_IMMU_PRIMARY_EXTENSION   0x48    /**< IMMU TSB primary extension register */
#define VA_IMMU_NUCLEUS_EXTENSION   0x58    /**< IMMU TSB nucleus extension register */
#endif
 
 
/* D-MMU ASIs. */
#define ASI_DMMU            0x58
#define ASI_DMMU_TSB_8KB_PTR_REG    0x59    
#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
#define ASI_DTLB_DATA_IN_REG        0x5c
#define ASI_DTLB_DATA_ACCESS_REG    0x5d
#define ASI_DTLB_TAG_READ_REG       0x5e
#define ASI_DMMU_DEMAP          0x5f
 
/* Virtual Addresses within ASI_DMMU. */
#define VA_DMMU_TSB_TAG_TARGET      0x0 /**< DMMU TSB tag target register. */
#define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
#define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
#define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
#if defined (US3)
#define VA_DMMU_PRIMARY_EXTENSION   0x48    /**< DMMU TSB primary extension register */
#define VA_DMMU_SECONDARY_EXTENSION 0x50    /**< DMMU TSB secondary extension register */
#define VA_DMMU_NUCLEUS_EXTENSION   0x58    /**< DMMU TSB nucleus extension register */
#endif
 
#ifndef __ASM__
 
#include <arch/asm.h>
#include <arch/barrier.h>
#include <arch/types.h>
 
#if defined(US)
/** LSU Control Register. */
typedef union {
    uint64_t value;
    struct {
        unsigned : 23;
        unsigned pm : 8;
        unsigned vm : 8;
        unsigned pr : 1;
        unsigned pw : 1;
        unsigned vr : 1;
        unsigned vw : 1;
        unsigned : 1;
        unsigned fm : 16;  
        unsigned dm : 1;    /**< D-MMU enable. */
        unsigned im : 1;    /**< I-MMU enable. */
        unsigned dc : 1;    /**< D-Cache enable. */
        unsigned ic : 1;    /**< I-Cache enable. */
       
    } __attribute__ ((packed));
} lsu_cr_reg_t;
#endif /* US */
 
#endif /* !def __ASM__ */
 
#endif
 
/** @}
 */
 

Rev 2927	Rev 3674
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64mm	29	/** @addtogroup sparc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_MMU_H_	35	#ifndef KERN_sparc64_MMU_H_
36	#define KERN_sparc64_MMU_H_	36	#define KERN_sparc64_MMU_H_
37		37
-		38	#if defined(US)
38	/* LSU Control Register ASI. */	39	/* LSU Control Register ASI. */
39	#define ASI_LSU_CONTROL_REG 0x45 /*< Load/Store Unit Control Register. /	40	#define ASI_LSU_CONTROL_REG 0x45 /*< Load/Store Unit Control Register. /
-		41	#endif
40		42
41	/* I-MMU ASIs. */	43	/* I-MMU ASIs. */
42	#define ASI_IMMU 0x50	44	#define ASI_IMMU 0x50
43	#define ASI_IMMU_TSB_8KB_PTR_REG 0x51	45	#define ASI_IMMU_TSB_8KB_PTR_REG 0x51
44	#define ASI_IMMU_TSB_64KB_PTR_REG 0x52	46	#define ASI_IMMU_TSB_64KB_PTR_REG 0x52
45	#define ASI_ITLB_DATA_IN_REG 0x54	47	#define ASI_ITLB_DATA_IN_REG 0x54
46	#define ASI_ITLB_DATA_ACCESS_REG 0x55	48	#define ASI_ITLB_DATA_ACCESS_REG 0x55
47	#define ASI_ITLB_TAG_READ_REG 0x56	49	#define ASI_ITLB_TAG_READ_REG 0x56
48	#define ASI_IMMU_DEMAP 0x57	50	#define ASI_IMMU_DEMAP 0x57
49		51
50	/* Virtual Addresses within ASI_IMMU. */	52	/* Virtual Addresses within ASI_IMMU. */
51	#define VA_IMMU_TSB_TAG_TARGET 0x0 /*< IMMU TSB tag target register. /	53	#define VA_IMMU_TSB_TAG_TARGET 0x0 /*< IMMU TSB tag target register. /
52	#define VA_IMMU_SFSR 0x18 /*< IMMU sync fault status register. /	54	#define VA_IMMU_SFSR 0x18 /*< IMMU sync fault status register. /
53	#define VA_IMMU_TSB_BASE 0x28 /*< IMMU TSB base register. /	55	#define VA_IMMU_TSB_BASE 0x28 /*< IMMU TSB base register. /
54	#define VA_IMMU_TAG_ACCESS 0x30 /*< IMMU TLB tag access register. /	56	#define VA_IMMU_TAG_ACCESS 0x30 /*< IMMU TLB tag access register. /
-		57	#if defined (US3)
-		58	#define VA_IMMU_PRIMARY_EXTENSION 0x48 /*< IMMU TSB primary extension register /
-		59	#define VA_IMMU_NUCLEUS_EXTENSION 0x58 /*< IMMU TSB nucleus extension register /
-		60	#endif
-		61
55		62
56	/* D-MMU ASIs. */	63	/* D-MMU ASIs. */
57	#define ASI_DMMU 0x58	64	#define ASI_DMMU 0x58
58	#define ASI_DMMU_TSB_8KB_PTR_REG 0x59	65	#define ASI_DMMU_TSB_8KB_PTR_REG 0x59
59	#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a	66	#define ASI_DMMU_TSB_64KB_PTR_REG 0x5a
60	#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b	67	#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
61	#define ASI_DTLB_DATA_IN_REG 0x5c	68	#define ASI_DTLB_DATA_IN_REG 0x5c
62	#define ASI_DTLB_DATA_ACCESS_REG 0x5d	69	#define ASI_DTLB_DATA_ACCESS_REG 0x5d
63	#define ASI_DTLB_TAG_READ_REG 0x5e	70	#define ASI_DTLB_TAG_READ_REG 0x5e
64	#define ASI_DMMU_DEMAP 0x5f	71	#define ASI_DMMU_DEMAP 0x5f
65		72
66	/* Virtual Addresses within ASI_DMMU. */	73	/* Virtual Addresses within ASI_DMMU. */
67	#define VA_DMMU_TSB_TAG_TARGET 0x0 /*< DMMU TSB tag target register. /	74	#define VA_DMMU_TSB_TAG_TARGET 0x0 /*< DMMU TSB tag target register. /
68	#define VA_PRIMARY_CONTEXT_REG 0x8 /*< DMMU primary context register. /	75	#define VA_PRIMARY_CONTEXT_REG 0x8 /*< DMMU primary context register. /
69	#define VA_SECONDARY_CONTEXT_REG 0x10 /*< DMMU secondary context register. /	76	#define VA_SECONDARY_CONTEXT_REG 0x10 /*< DMMU secondary context register. /
70	#define VA_DMMU_SFSR 0x18 /*< DMMU sync fault status register. /	77	#define VA_DMMU_SFSR 0x18 /*< DMMU sync fault status register. /
71	#define VA_DMMU_SFAR 0x20 /*< DMMU sync fault address register. /	78	#define VA_DMMU_SFAR 0x20 /*< DMMU sync fault address register. /
72	#define VA_DMMU_TSB_BASE 0x28 /*< DMMU TSB base register. /	79	#define VA_DMMU_TSB_BASE 0x28 /*< DMMU TSB base register. /
73	#define VA_DMMU_TAG_ACCESS 0x30 /*< DMMU TLB tag access register. /	80	#define VA_DMMU_TAG_ACCESS 0x30 /*< DMMU TLB tag access register. /
74	#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /*< DMMU VA data watchpoint register. /	81	#define VA_DMMU_VA_WATCHPOINT_REG 0x38 /*< DMMU VA data watchpoint register. /
75	#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /*< DMMU PA data watchpoint register. /	82	#define VA_DMMU_PA_WATCHPOINT_REG 0x40 /*< DMMU PA data watchpoint register. /
-		83	#if defined (US3)
-		84	#define VA_DMMU_PRIMARY_EXTENSION 0x48 /*< DMMU TSB primary extension register /
-		85	#define VA_DMMU_SECONDARY_EXTENSION 0x50 /*< DMMU TSB secondary extension register /
-		86	#define VA_DMMU_NUCLEUS_EXTENSION 0x58 /*< DMMU TSB nucleus extension register /
-		87	#endif
76		88
77	#ifndef __ASM__	89	#ifndef __ASM__
78		90
79	#include <arch/asm.h>	91	#include <arch/asm.h>
80	#include <arch/barrier.h>	92	#include <arch/barrier.h>
81	#include <arch/types.h>	93	#include <arch/types.h>
82		94
-		95	#if defined(US)
83	/** LSU Control Register. */	96	/** LSU Control Register. */
84	typedef union {	97	typedef union {
85	uint64_t value;	98	uint64_t value;
86	struct {	99	struct {
87	unsigned : 23;	100	unsigned : 23;
88	unsigned pm : 8;	101	unsigned pm : 8;
89	unsigned vm : 8;	102	unsigned vm : 8;
90	unsigned pr : 1;	103	unsigned pr : 1;
91	unsigned pw : 1;	104	unsigned pw : 1;
92	unsigned vr : 1;	105	unsigned vr : 1;
93	unsigned vw : 1;	106	unsigned vw : 1;
94	unsigned : 1;	107	unsigned : 1;
95	unsigned fm : 16;	108	unsigned fm : 16;
96	unsigned dm : 1; /*< D-MMU enable. /	109	unsigned dm : 1; /*< D-MMU enable. /
97	unsigned im : 1; /*< I-MMU enable. /	110	unsigned im : 1; /*< I-MMU enable. /
98	unsigned dc : 1; /*< D-Cache enable. /	111	unsigned dc : 1; /*< D-Cache enable. /
99	unsigned ic : 1; /*< I-Cache enable. /	112	unsigned ic : 1; /*< I-Cache enable. /
100		113
101	} __attribute__ ((packed));	114	} __attribute__ ((packed));
102	} lsu_cr_reg_t;	115	} lsu_cr_reg_t;
-		116	#endif /* US */
103		117
104	#endif /* !def __ASM__ */	118	#endif /* !def __ASM__ */
105		119
106	#endif	120	#endif
107		121
108	/** @}	122	/** @}
109	*/	123	*/
110		124

Subversion Repositories HelenOS

(root)/branches/dynload/kernel/arch/sparc64/include/mm/mmu.h – Rev 2927 → 3674