WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/sparc64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup sparc64
 * @{
 */
/** @file
 */
 
#ifndef KERN_sparc64_ASM_H_
#define KERN_sparc64_ASM_H_
 
#include <arch/arch.h>
#include <arch/types.h>
#include <typedefs.h>
#include <align.h>
#include <arch/register.h>
#include <config.h>
#include <arch/stack.h>
#include <arch/barrier.h>
 
static inline void outb(ioport_t port, uint8_t v)
{
    *((volatile uint8_t *)(port)) = v;
    memory_barrier();
}
 
static inline void outw(ioport_t port, uint16_t v)
{
    *((volatile uint16_t *)(port)) = v;
    memory_barrier();
}
 
static inline void outl(ioport_t port, uint32_t v)
{
    *((volatile uint32_t *)(port)) = v;
    memory_barrier();
}
 
static inline uint8_t inb(ioport_t port)
{
    uint8_t rv;
 
    rv = *((volatile uint8_t *)(port));
    memory_barrier();
 
    return rv;
}
 
static inline uint16_t inw(ioport_t port)
{
    uint16_t rv;
 
    rv = *((volatile uint16_t *)(port));
    memory_barrier();
 
    return rv;
}
 
static inline uint32_t inl(ioport_t port)
{
    uint32_t rv;
 
    rv = *((volatile uint32_t *)(port));
    memory_barrier();
 
    return rv;
}
 
/** Read Processor State register.
 *
 * @return Value of PSTATE register.
 */
static inline uint64_t pstate_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Processor State register.
 *
 * @param v New value of PSTATE register.
 */
static inline void pstate_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
}
 
/** Read TICK_compare Register.
 *
 * @return Value of TICK_comapre register.
 */
static inline uint64_t tick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK_compare Register.
 *
 * @param v New value of TICK_comapre register.
 */
static inline void tick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
}
 
/** Read STICK_compare Register.
 *
 * @return Value of STICK_compare register.
 */
static inline uint64_t stick_compare_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%asr25, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write STICK_compare Register.
 *
 * @param v New value of STICK_comapre register.
 */
static inline void stick_compare_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
}
 
/** Read TICK Register.
 *
 * @return Value of TICK register.
 */
static inline uint64_t tick_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write TICK Register.
 *
 * @param v New value of TICK register.
 */
static inline void tick_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
}
 
/** Read FPRS Register.
 *
 * @return Value of FPRS register.
 */
static inline uint64_t fprs_read(void)
{
    uint64_t v;
   
    asm volatile ("rd %%fprs, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write FPRS Register.
 *
 * @param v New value of FPRS register.
 */
static inline void fprs_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
}
 
/** Read SOFTINT Register.
 *
 * @return Value of SOFTINT register.
 */
static inline uint64_t softint_read(void)
{
    uint64_t v;
 
    asm volatile ("rd %%softint, %0\n" : "=r" (v));
 
    return v;
}
 
/** Write SOFTINT Register.
 *
 * @param v New value of SOFTINT register.
 */
static inline void softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
}
 
/** Write CLEAR_SOFTINT Register.
 *
 * Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
 *
 * @param v New value of CLEAR_SOFTINT register.
 */
static inline void clear_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
}
 
/** Write SET_SOFTINT Register.
 *
 * Bits set in SET_SOFTINT register will be set in SOFTINT register.
 *
 * @param v New value of SET_SOFTINT register.
 */
static inline void set_softint_write(uint64_t v)
{
    asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = true;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of IPL.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void) {
    pstate_reg_t pstate;
    uint64_t value;
   
    value = pstate_read();
    pstate.value = value;
    pstate.ie = false;
    pstate_write(pstate.value);
   
    return (ipl_t) value;
}
 
/** Restore interrupt priority level.
 *
 * Restore IPL.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl) {
    pstate_reg_t pstate;
   
    pstate.value = pstate_read();
    pstate.ie = ((pstate_reg_t) ipl).ie;
    pstate_write(pstate.value);
}
 
/** Return interrupt priority level.
 *
 * Return IPL.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void) {
    return (ipl_t) pstate_read();
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t unbiased_sp;
   
    asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
   
    return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
}
 
/** Read Version Register.
 *
 * @return Value of VER register.
 */
static inline uint64_t ver_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Program Counter register.
 *
 * @return Current value in TPC.
 */
static inline uint64_t tpc_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Level register.
 *
 * @return Current value in TL.
 */
static inline uint64_t tl_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
   
    return v;
}
 
/** Read Trap Base Address register.
 *
 * @return Current value in TBA.
 */
static inline uint64_t tba_read(void)
{
    uint64_t v;
   
    asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
   
    return v;
}
 
/** Write Trap Base Address register.
 *
 * @param v New value of TBA.
 */
static inline void tba_write(uint64_t v)
{
    asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
}
 
/** Load uint64_t from alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 *
 * @return Value read from the virtual address in the specified address space.
 */
static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
{
    uint64_t v;
   
    asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
   
    return v;
}
 
/** Store uint64_t to alternate space.
 *
 * @param asi ASI determining the alternate space.
 * @param va Virtual address within the ASI.
 * @param v Value to be written.
 */
static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
{
    asm volatile ("stxa %0, [%1] %2\n" : :  "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
}
 
/** Flush all valid register windows to memory. */
static inline void flushw(void)
{
    asm volatile ("flushw\n");
}
 
/** Switch to nucleus by setting TL to 1. */
static inline void nucleus_enter(void)
{
    asm volatile ("wrpr %g0, 1, %tl\n");
}
 
/** Switch from nucleus by setting TL to 0. */
static inline void nucleus_leave(void)
{
    asm volatile ("wrpr %g0, %g0, %tl\n");
}
 
 
 
 
 
 
 
 
 
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(const uint32_t usec);
 
extern uint64_t read_from_ag_g7(void);
extern void write_to_ag_g6(uint64_t val);
extern void write_to_ag_g7(uint64_t val);
extern void write_to_ig_g6(uint64_t val);
 
extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
 
#endif
 
/** @}
 */
 

Rev 3588	Rev 3674
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup sparc64	29	/** @addtogroup sparc64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_sparc64_ASM_H_	35	#ifndef KERN_sparc64_ASM_H_
36	#define KERN_sparc64_ASM_H_	36	#define KERN_sparc64_ASM_H_
37		37
38	#include <arch/arch.h>	38	#include <arch/arch.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <typedefs.h>	40	#include <typedefs.h>
41	#include <align.h>	41	#include <align.h>
42	#include <arch/register.h>	42	#include <arch/register.h>
43	#include <config.h>	43	#include <config.h>
44	#include <arch/stack.h>	44	#include <arch/stack.h>
45	#include <arch/barrier.h>	45	#include <arch/barrier.h>
46		46
47	static inline void outb(ioport_t port, uint8_t v)	47	static inline void outb(ioport_t port, uint8_t v)
48	{	48	{
49	((volatile uint8_t )(port)) = v;	49	((volatile uint8_t )(port)) = v;
50	memory_barrier();	50	memory_barrier();
51	}	51	}
52		52
53	static inline void outw(ioport_t port, uint16_t v)	53	static inline void outw(ioport_t port, uint16_t v)
54	{	54	{
55	((volatile uint16_t )(port)) = v;	55	((volatile uint16_t )(port)) = v;
56	memory_barrier();	56	memory_barrier();
57	}	57	}
58		58
59	static inline void outl(ioport_t port, uint32_t v)	59	static inline void outl(ioport_t port, uint32_t v)
60	{	60	{
61	((volatile uint32_t )(port)) = v;	61	((volatile uint32_t )(port)) = v;
62	memory_barrier();	62	memory_barrier();
63	}	63	}
64		64
65	static inline uint8_t inb(ioport_t port)	65	static inline uint8_t inb(ioport_t port)
66	{	66	{
67	uint8_t rv;	67	uint8_t rv;
68		68
69	rv = ((volatile uint8_t )(port));	69	rv = ((volatile uint8_t )(port));
70	memory_barrier();	70	memory_barrier();
71		71
72	return rv;	72	return rv;
73	}	73	}
74		74
75	static inline uint16_t inw(ioport_t port)	75	static inline uint16_t inw(ioport_t port)
76	{	76	{
77	uint16_t rv;	77	uint16_t rv;
78		78
79	rv = ((volatile uint16_t )(port));	79	rv = ((volatile uint16_t )(port));
80	memory_barrier();	80	memory_barrier();
81		81
82	return rv;	82	return rv;
83	}	83	}
84		84
85	static inline uint32_t inl(ioport_t port)	85	static inline uint32_t inl(ioport_t port)
86	{	86	{
87	uint32_t rv;	87	uint32_t rv;
88		88
89	rv = ((volatile uint32_t )(port));	89	rv = ((volatile uint32_t )(port));
90	memory_barrier();	90	memory_barrier();
91		91
92	return rv;	92	return rv;
93	}	93	}
94		94
95	/** Read Processor State register.	95	/** Read Processor State register.
96	*	96	*
97	* @return Value of PSTATE register.	97	* @return Value of PSTATE register.
98	*/	98	*/
99	static inline uint64_t pstate_read(void)	99	static inline uint64_t pstate_read(void)
100	{	100	{
101	uint64_t v;	101	uint64_t v;
102		102
103	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));	103	asm volatile ("rdpr %%pstate, %0\n" : "=r" (v));
104		104
105	return v;	105	return v;
106	}	106	}
107		107
108	/** Write Processor State register.	108	/** Write Processor State register.
109	*	109	*
110	* @param v New value of PSTATE register.	110	* @param v New value of PSTATE register.
111	*/	111	*/
112	static inline void pstate_write(uint64_t v)	112	static inline void pstate_write(uint64_t v)
113	{	113	{
114	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));	114	asm volatile ("wrpr %0, %1, %%pstate\n" : : "r" (v), "i" (0));
115	}	115	}
116		116
117	/** Read TICK_compare Register.	117	/** Read TICK_compare Register.
118	*	118	*
119	* @return Value of TICK_comapre register.	119	* @return Value of TICK_comapre register.
120	*/	120	*/
121	static inline uint64_t tick_compare_read(void)	121	static inline uint64_t tick_compare_read(void)
122	{	122	{
123	uint64_t v;	123	uint64_t v;
124		124
125	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));	125	asm volatile ("rd %%tick_cmpr, %0\n" : "=r" (v));
126		126
127	return v;	127	return v;
128	}	128	}
129		129
130	/** Write TICK_compare Register.	130	/** Write TICK_compare Register.
131	*	131	*
132	* @param v New value of TICK_comapre register.	132	* @param v New value of TICK_comapre register.
133	*/	133	*/
134	static inline void tick_compare_write(uint64_t v)	134	static inline void tick_compare_write(uint64_t v)
135	{	135	{
136	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));	136	asm volatile ("wr %0, %1, %%tick_cmpr\n" : : "r" (v), "i" (0));
137	}	137	}
138		138
-		139	/** Read STICK_compare Register.
-		140	*
-		141	* @return Value of STICK_compare register.
-		142	*/
-		143	static inline uint64_t stick_compare_read(void)
-		144	{
-		145	uint64_t v;
-		146
-		147	asm volatile ("rd %%asr25, %0\n" : "=r" (v));
-		148
-		149	return v;
-		150	}
-		151
-		152	/** Write STICK_compare Register.
-		153	*
-		154	* @param v New value of STICK_comapre register.
-		155	*/
-		156	static inline void stick_compare_write(uint64_t v)
-		157	{
-		158	asm volatile ("wr %0, %1, %%asr25\n" : : "r" (v), "i" (0));
-		159	}
-		160
139	/** Read TICK Register.	161	/** Read TICK Register.
140	*	162	*
141	* @return Value of TICK register.	163	* @return Value of TICK register.
142	*/	164	*/
143	static inline uint64_t tick_read(void)	165	static inline uint64_t tick_read(void)
144	{	166	{
145	uint64_t v;	167	uint64_t v;
146		168
147	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));	169	asm volatile ("rdpr %%tick, %0\n" : "=r" (v));
148		170
149	return v;	171	return v;
150	}	172	}
151		173
152	/** Write TICK Register.	174	/** Write TICK Register.
153	*	175	*
154	* @param v New value of TICK register.	176	* @param v New value of TICK register.
155	*/	177	*/
156	static inline void tick_write(uint64_t v)	178	static inline void tick_write(uint64_t v)
157	{	179	{
158	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));	180	asm volatile ("wrpr %0, %1, %%tick\n" : : "r" (v), "i" (0));
159	}	181	}
160		182
161	/** Read FPRS Register.	183	/** Read FPRS Register.
162	*	184	*
163	* @return Value of FPRS register.	185	* @return Value of FPRS register.
164	*/	186	*/
165	static inline uint64_t fprs_read(void)	187	static inline uint64_t fprs_read(void)
166	{	188	{
167	uint64_t v;	189	uint64_t v;
168		190
169	asm volatile ("rd %%fprs, %0\n" : "=r" (v));	191	asm volatile ("rd %%fprs, %0\n" : "=r" (v));
170		192
171	return v;	193	return v;
172	}	194	}
173		195
174	/** Write FPRS Register.	196	/** Write FPRS Register.
175	*	197	*
176	* @param v New value of FPRS register.	198	* @param v New value of FPRS register.
177	*/	199	*/
178	static inline void fprs_write(uint64_t v)	200	static inline void fprs_write(uint64_t v)
179	{	201	{
180	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));	202	asm volatile ("wr %0, %1, %%fprs\n" : : "r" (v), "i" (0));
181	}	203	}
182		204
183	/** Read SOFTINT Register.	205	/** Read SOFTINT Register.
184	*	206	*
185	* @return Value of SOFTINT register.	207	* @return Value of SOFTINT register.
186	*/	208	*/
187	static inline uint64_t softint_read(void)	209	static inline uint64_t softint_read(void)
188	{	210	{
189	uint64_t v;	211	uint64_t v;
190		212
191	asm volatile ("rd %%softint, %0\n" : "=r" (v));	213	asm volatile ("rd %%softint, %0\n" : "=r" (v));
192		214
193	return v;	215	return v;
194	}	216	}
195		217
196	/** Write SOFTINT Register.	218	/** Write SOFTINT Register.
197	*	219	*
198	* @param v New value of SOFTINT register.	220	* @param v New value of SOFTINT register.
199	*/	221	*/
200	static inline void softint_write(uint64_t v)	222	static inline void softint_write(uint64_t v)
201	{	223	{
202	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));	224	asm volatile ("wr %0, %1, %%softint\n" : : "r" (v), "i" (0));
203	}	225	}
204		226
205	/** Write CLEAR_SOFTINT Register.	227	/** Write CLEAR_SOFTINT Register.
206	*	228	*
207	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.	229	* Bits set in CLEAR_SOFTINT register will be cleared in SOFTINT register.
208	*	230	*
209	* @param v New value of CLEAR_SOFTINT register.	231	* @param v New value of CLEAR_SOFTINT register.
210	*/	232	*/
211	static inline void clear_softint_write(uint64_t v)	233	static inline void clear_softint_write(uint64_t v)
212	{	234	{
213	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));	235	asm volatile ("wr %0, %1, %%clear_softint\n" : : "r" (v), "i" (0));
214	}	236	}
215		237
216	/** Write SET_SOFTINT Register.	238	/** Write SET_SOFTINT Register.
217	*	239	*
218	* Bits set in SET_SOFTINT register will be set in SOFTINT register.	240	* Bits set in SET_SOFTINT register will be set in SOFTINT register.
219	*	241	*
220	* @param v New value of SET_SOFTINT register.	242	* @param v New value of SET_SOFTINT register.
221	*/	243	*/
222	static inline void set_softint_write(uint64_t v)	244	static inline void set_softint_write(uint64_t v)
223	{	245	{
224	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));	246	asm volatile ("wr %0, %1, %%set_softint\n" : : "r" (v), "i" (0));
225	}	247	}
226		248
227	/** Enable interrupts.	249	/** Enable interrupts.
228	*	250	*
229	* Enable interrupts and return previous	251	* Enable interrupts and return previous
230	* value of IPL.	252	* value of IPL.
231	*	253	*
232	* @return Old interrupt priority level.	254	* @return Old interrupt priority level.
233	*/	255	*/
234	static inline ipl_t interrupts_enable(void) {	256	static inline ipl_t interrupts_enable(void) {
235	pstate_reg_t pstate;	257	pstate_reg_t pstate;
236	uint64_t value;	258	uint64_t value;
237		259
238	value = pstate_read();	260	value = pstate_read();
239	pstate.value = value;	261	pstate.value = value;
240	pstate.ie = true;	262	pstate.ie = true;
241	pstate_write(pstate.value);	263	pstate_write(pstate.value);
242		264
243	return (ipl_t) value;	265	return (ipl_t) value;
244	}	266	}
245		267
246	/** Disable interrupts.	268	/** Disable interrupts.
247	*	269	*
248	* Disable interrupts and return previous	270	* Disable interrupts and return previous
249	* value of IPL.	271	* value of IPL.
250	*	272	*
251	* @return Old interrupt priority level.	273	* @return Old interrupt priority level.
252	*/	274	*/
253	static inline ipl_t interrupts_disable(void) {	275	static inline ipl_t interrupts_disable(void) {
254	pstate_reg_t pstate;	276	pstate_reg_t pstate;
255	uint64_t value;	277	uint64_t value;
256		278
257	value = pstate_read();	279	value = pstate_read();
258	pstate.value = value;	280	pstate.value = value;
259	pstate.ie = false;	281	pstate.ie = false;
260	pstate_write(pstate.value);	282	pstate_write(pstate.value);
261		283
262	return (ipl_t) value;	284	return (ipl_t) value;
263	}	285	}
264		286
265	/** Restore interrupt priority level.	287	/** Restore interrupt priority level.
266	*	288	*
267	* Restore IPL.	289	* Restore IPL.
268	*	290	*
269	* @param ipl Saved interrupt priority level.	291	* @param ipl Saved interrupt priority level.
270	*/	292	*/
271	static inline void interrupts_restore(ipl_t ipl) {	293	static inline void interrupts_restore(ipl_t ipl) {
272	pstate_reg_t pstate;	294	pstate_reg_t pstate;
273		295
274	pstate.value = pstate_read();	296	pstate.value = pstate_read();
275	pstate.ie = ((pstate_reg_t) ipl).ie;	297	pstate.ie = ((pstate_reg_t) ipl).ie;
276	pstate_write(pstate.value);	298	pstate_write(pstate.value);
277	}	299	}
278		300
279	/** Return interrupt priority level.	301	/** Return interrupt priority level.
280	*	302	*
281	* Return IPL.	303	* Return IPL.
282	*	304	*
283	* @return Current interrupt priority level.	305	* @return Current interrupt priority level.
284	*/	306	*/
285	static inline ipl_t interrupts_read(void) {	307	static inline ipl_t interrupts_read(void) {
286	return (ipl_t) pstate_read();	308	return (ipl_t) pstate_read();
287	}	309	}
288		310
289	/** Return base address of current stack.	311	/** Return base address of current stack.
290	*	312	*
291	* Return the base address of the current stack.	313	* Return the base address of the current stack.
292	* The stack is assumed to be STACK_SIZE bytes long.	314	* The stack is assumed to be STACK_SIZE bytes long.
293	* The stack must start on page boundary.	315	* The stack must start on page boundary.
294	*/	316	*/
295	static inline uintptr_t get_stack_base(void)	317	static inline uintptr_t get_stack_base(void)
296	{	318	{
297	uintptr_t unbiased_sp;	319	uintptr_t unbiased_sp;
298		320
299	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));	321	asm volatile ("add %%sp, %1, %0\n" : "=r" (unbiased_sp) : "i" (STACK_BIAS));
300		322
301	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);	323	return ALIGN_DOWN(unbiased_sp, STACK_SIZE);
302	}	324	}
303		325
304	/** Read Version Register.	326	/** Read Version Register.
305	*	327	*
306	* @return Value of VER register.	328	* @return Value of VER register.
307	*/	329	*/
308	static inline uint64_t ver_read(void)	330	static inline uint64_t ver_read(void)
309	{	331	{
310	uint64_t v;	332	uint64_t v;
311		333
312	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));	334	asm volatile ("rdpr %%ver, %0\n" : "=r" (v));
313		335
314	return v;	336	return v;
315	}	337	}
316		338
317	/** Read Trap Program Counter register.	339	/** Read Trap Program Counter register.
318	*	340	*
319	* @return Current value in TPC.	341	* @return Current value in TPC.
320	*/	342	*/
321	static inline uint64_t tpc_read(void)	343	static inline uint64_t tpc_read(void)
322	{	344	{
323	uint64_t v;	345	uint64_t v;
324		346
325	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));	347	asm volatile ("rdpr %%tpc, %0\n" : "=r" (v));
326		348
327	return v;	349	return v;
328	}	350	}
329		351
330	/** Read Trap Level register.	352	/** Read Trap Level register.
331	*	353	*
332	* @return Current value in TL.	354	* @return Current value in TL.
333	*/	355	*/
334	static inline uint64_t tl_read(void)	356	static inline uint64_t tl_read(void)
335	{	357	{
336	uint64_t v;	358	uint64_t v;
337		359
338	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));	360	asm volatile ("rdpr %%tl, %0\n" : "=r" (v));
339		361
340	return v;	362	return v;
341	}	363	}
342		364
343	/** Read Trap Base Address register.	365	/** Read Trap Base Address register.
344	*	366	*
345	* @return Current value in TBA.	367	* @return Current value in TBA.
346	*/	368	*/
347	static inline uint64_t tba_read(void)	369	static inline uint64_t tba_read(void)
348	{	370	{
349	uint64_t v;	371	uint64_t v;
350		372
351	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));	373	asm volatile ("rdpr %%tba, %0\n" : "=r" (v));
352		374
353	return v;	375	return v;
354	}	376	}
355		377
356	/** Write Trap Base Address register.	378	/** Write Trap Base Address register.
357	*	379	*
358	* @param v New value of TBA.	380	* @param v New value of TBA.
359	*/	381	*/
360	static inline void tba_write(uint64_t v)	382	static inline void tba_write(uint64_t v)
361	{	383	{
362	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));	384	asm volatile ("wrpr %0, %1, %%tba\n" : : "r" (v), "i" (0));
363	}	385	}
364		386
365	/** Load uint64_t from alternate space.	387	/** Load uint64_t from alternate space.
366	*	388	*
367	* @param asi ASI determining the alternate space.	389	* @param asi ASI determining the alternate space.
368	* @param va Virtual address within the ASI.	390	* @param va Virtual address within the ASI.
369	*	391	*
370	* @return Value read from the virtual address in the specified address space.	392	* @return Value read from the virtual address in the specified address space.
371	*/	393	*/
372	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)	394	static inline uint64_t asi_u64_read(asi_t asi, uintptr_t va)
373	{	395	{
374	uint64_t v;	396	uint64_t v;
375		397
376	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));	398	asm volatile ("ldxa [%1] %2, %0\n" : "=r" (v) : "r" (va), "i" ((unsigned) asi));
377		399
378	return v;	400	return v;
379	}	401	}
380		402
381	/** Store uint64_t to alternate space.	403	/** Store uint64_t to alternate space.
382	*	404	*
383	* @param asi ASI determining the alternate space.	405	* @param asi ASI determining the alternate space.
384	* @param va Virtual address within the ASI.	406	* @param va Virtual address within the ASI.
385	* @param v Value to be written.	407	* @param v Value to be written.
386	*/	408	*/
387	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)	409	static inline void asi_u64_write(asi_t asi, uintptr_t va, uint64_t v)
388	{	410	{
389	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");	411	asm volatile ("stxa %0, [%1] %2\n" : : "r" (v), "r" (va), "i" ((unsigned) asi) : "memory");
390	}	412	}
391		413
392	/** Flush all valid register windows to memory. */	414	/** Flush all valid register windows to memory. */
393	static inline void flushw(void)	415	static inline void flushw(void)
394	{	416	{
395	asm volatile ("flushw\n");	417	asm volatile ("flushw\n");
396	}	418	}
397		419
398	/** Switch to nucleus by setting TL to 1. */	420	/** Switch to nucleus by setting TL to 1. */
399	static inline void nucleus_enter(void)	421	static inline void nucleus_enter(void)
400	{	422	{
401	asm volatile ("wrpr %g0, 1, %tl\n");	423	asm volatile ("wrpr %g0, 1, %tl\n");
402	}	424	}
403		425
404	/** Switch from nucleus by setting TL to 0. */	426	/** Switch from nucleus by setting TL to 0. */
405	static inline void nucleus_leave(void)	427	static inline void nucleus_leave(void)
406	{	428	{
407	asm volatile ("wrpr %g0, %g0, %tl\n");	429	asm volatile ("wrpr %g0, %g0, %tl\n");
408	}	430	}
409		-
410	/** Read UPA_CONFIG register.	-
411	*	-
412	* @return Value of the UPA_CONFIG register.	-
413	*/	-
414	static inline uint64_t upa_config_read(void)	-
415	{	-
416	return asi_u64_read(ASI_UPA_CONFIG, 0);	-
417	}	-
418		431
419	extern void cpu_halt(void);	432	extern void cpu_halt(void);
420	extern void cpu_sleep(void);	433	extern void cpu_sleep(void);
421	extern void asm_delay_loop(const uint32_t usec);	434	extern void asm_delay_loop(const uint32_t usec);
422		435
423	extern uint64_t read_from_ag_g7(void);	436	extern uint64_t read_from_ag_g7(void);
424	extern void write_to_ag_g6(uint64_t val);	437	extern void write_to_ag_g6(uint64_t val);
425	extern void write_to_ag_g7(uint64_t val);	438	extern void write_to_ag_g7(uint64_t val);
426	extern void write_to_ig_g6(uint64_t val);	439	extern void write_to_ig_g6(uint64_t val);
427		440
428	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);	441	extern void switch_to_userspace(uint64_t pc, uint64_t sp, uint64_t uarg);
429		442
430	#endif	443	#endif
431		444
432	/** @}	445	/** @}
433	*/	446	*/
434		447

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(root)/branches/dynload/kernel/arch/sparc64/include/asm.h – Rev 3588 → 3674