WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/ppc64/include/mm/page.h


/*
 * Copyright (c) 2005 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc64mm
 * @{
 */
/** @file
 */
 
#ifndef KERN_ppc64_PAGE_H_
#define KERN_ppc64_PAGE_H_
 
#include <arch/mm/frame.h>
 
#define PAGE_WIDTH  FRAME_WIDTH
#define PAGE_SIZE   FRAME_SIZE
 
 
 
#ifdef KERNEL
 
#ifndef __ASM__
#   define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
#   define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
#else
#   define KA2PA(x) ((x) - 0x80000000)
#   define PA2KA(x) ((x) + 0x80000000)
#endif
 
/*
 * Implementation of generic 4-level page table interface,
 * the hardware Page Hash Table is used as cache.
 *
 * Page table layout:
 * - 32-bit virtual addressess
 * - Offset is 12 bits => pages are 4K long
 * - PTL0 has 1024 entries (10 bits)
 * - PTL1 is not used
 * - PTL2 is not used
 * - PLT3 has 1024 entries (10 bits)
 */
 
/* Number of entries in each level. */
#define PTL0_ENTRIES_ARCH   1024
#define PTL1_ENTRIES_ARCH   0
#define PTL2_ENTRIES_ARCH   0
#define PTL3_ENTRIES_ARCH   1024
 
/* Sizes of page tables in each level. */
#define PTL0_SIZE_ARCH      ONE_FRAME
#define PTL1_SIZE_ARCH      0
#define PTL2_SIZE_ARCH      0
#define PTL3_SIZE_ARCH      ONE_FRAME
 
/* Macros calculating indices into page tables in each level. */
#define PTL0_INDEX_ARCH(vaddr)  (((vaddr) >> 22) & 0x3ff)
#define PTL1_INDEX_ARCH(vaddr)  0
#define PTL2_INDEX_ARCH(vaddr)  0
#define PTL3_INDEX_ARCH(vaddr)  (((vaddr) >> 12) & 0x3ff)
 
/* Get PTE address accessors for each level. */
#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
    (((pte_t *) (ptl0))[(i)].pfn << 12)
#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
    (ptl1)
#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
    (ptl2)
#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
    (((pte_t *) (ptl3))[(i)].pfn << 12)
 
/* Set PTE address accessors for each level. */
#define SET_PTL0_ADDRESS_ARCH(ptl0)
#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
    (((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
    (((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
 
/* Get PTE flags accessors for each level. */
#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
    get_pt_flags((pte_t *) (ptl0), (index_t) (i))
#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
    PAGE_PRESENT
#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
    PAGE_PRESENT
#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
    get_pt_flags((pte_t *) (ptl3), (index_t) (i))
 
/* Set PTE flags accessors for each level. */
#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
    set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
    set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
 
/* Macros for querying the last-level PTEs. */
#define PTE_VALID_ARCH(pte)         (*((uint32_t *) (pte)) != 0)
#define PTE_PRESENT_ARCH(pte)           ((pte)->p != 0)
#define PTE_GET_FRAME_ARCH(pte)         ((uintptr_t) ((pte)->pfn << 12))
#define PTE_WRITABLE_ARCH(pte)          1
#define PTE_EXECUTABLE_ARCH(pte)        1
 
#ifndef __ASM__
 
#include <mm/mm.h>
#include <arch/interrupt.h>
 
static inline int get_pt_flags(pte_t *pt, index_t i)
{
    pte_t *p = &pt[i];
   
    return ((1 << PAGE_CACHEABLE_SHIFT) |
        ((!p->p) << PAGE_PRESENT_SHIFT) |
        (1 << PAGE_USER_SHIFT) |
        (1 << PAGE_READ_SHIFT) |
        (1 << PAGE_WRITE_SHIFT) |
        (1 << PAGE_EXEC_SHIFT) |
        (p->g << PAGE_GLOBAL_SHIFT));
}
 
static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
{
    pte_t *p = &pt[i];
   
    p->p = !(flags & PAGE_NOT_PRESENT);
    p->g = (flags & PAGE_GLOBAL) != 0;
    p->valid = 1;
}
 
extern void page_arch_init(void);
 
#define PHT_BITS    16
#define PHT_ORDER   4
 
typedef struct {
    unsigned v : 1;          /**< Valid */
    unsigned vsid : 24;      /**< Virtual Segment ID */
    unsigned h : 1;          /**< Primary/secondary hash */
    unsigned api : 6;        /**< Abbreviated Page Index */
    unsigned rpn : 20;       /**< Real Page Number */
    unsigned reserved0 : 3;
    unsigned r : 1;          /**< Reference */
    unsigned c : 1;          /**< Change */
    unsigned wimg : 4;       /**< Access control */
    unsigned reserved1 : 1;
    unsigned pp : 2;         /**< Page protection */
} phte_t;
 
extern void pht_refill(bool data, istate_t *istate);
extern void pht_init(void);
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/branches/dynload/kernel/arch/ppc64/include/mm/page.h – Rev 2927 → 3403

Rev 2927		Rev 3403
1	/*	1	/*
2	* Copyright (c) 2005 Martin Decky	2	* Copyright (c) 2005 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc64mm	29	/** @addtogroup ppc64mm
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ppc64_PAGE_H_	35	#ifndef KERN_ppc64_PAGE_H_
36	#define KERN_ppc64_PAGE_H_	36	#define KERN_ppc64_PAGE_H_
37		37
38	#include <arch/mm/frame.h>	38	#include <arch/mm/frame.h>
39		39
40	#define PAGE_WIDTH FRAME_WIDTH	40	#define PAGE_WIDTH FRAME_WIDTH
41	#define PAGE_SIZE FRAME_SIZE	41	#define PAGE_SIZE FRAME_SIZE
42		42
43	#define PAGE_COLOR_BITS 0 /* dummy */	-
44		-
45	#ifdef KERNEL	43	#ifdef KERNEL
46		44
47	#ifndef __ASM__	45	#ifndef __ASM__
48	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)	46	# define KA2PA(x) (((uintptr_t) (x)) - 0x80000000)
49	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)	47	# define PA2KA(x) (((uintptr_t) (x)) + 0x80000000)
50	#else	48	#else
51	# define KA2PA(x) ((x) - 0x80000000)	49	# define KA2PA(x) ((x) - 0x80000000)
52	# define PA2KA(x) ((x) + 0x80000000)	50	# define PA2KA(x) ((x) + 0x80000000)
53	#endif	51	#endif
54		52
55	/*	53	/*
56	* Implementation of generic 4-level page table interface,	54	* Implementation of generic 4-level page table interface,
57	* the hardware Page Hash Table is used as cache.	55	* the hardware Page Hash Table is used as cache.
58	*	56	*
59	* Page table layout:	57	* Page table layout:
60	* - 32-bit virtual addressess	58	* - 32-bit virtual addressess
61	* - Offset is 12 bits => pages are 4K long	59	* - Offset is 12 bits => pages are 4K long
62	* - PTL0 has 1024 entries (10 bits)	60	* - PTL0 has 1024 entries (10 bits)
63	* - PTL1 is not used	61	* - PTL1 is not used
64	* - PTL2 is not used	62	* - PTL2 is not used
65	* - PLT3 has 1024 entries (10 bits)	63	* - PLT3 has 1024 entries (10 bits)
66	*/	64	*/
67		65
68	/* Number of entries in each level. */	66	/* Number of entries in each level. */
69	#define PTL0_ENTRIES_ARCH 1024	67	#define PTL0_ENTRIES_ARCH 1024
70	#define PTL1_ENTRIES_ARCH 0	68	#define PTL1_ENTRIES_ARCH 0
71	#define PTL2_ENTRIES_ARCH 0	69	#define PTL2_ENTRIES_ARCH 0
72	#define PTL3_ENTRIES_ARCH 1024	70	#define PTL3_ENTRIES_ARCH 1024
73		71
74	/* Sizes of page tables in each level. */	72	/* Sizes of page tables in each level. */
75	#define PTL0_SIZE_ARCH ONE_FRAME	73	#define PTL0_SIZE_ARCH ONE_FRAME
76	#define PTL1_SIZE_ARCH 0	74	#define PTL1_SIZE_ARCH 0
77	#define PTL2_SIZE_ARCH 0	75	#define PTL2_SIZE_ARCH 0
78	#define PTL3_SIZE_ARCH ONE_FRAME	76	#define PTL3_SIZE_ARCH ONE_FRAME
79		77
80	/* Macros calculating indices into page tables in each level. */	78	/* Macros calculating indices into page tables in each level. */
81	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)	79	#define PTL0_INDEX_ARCH(vaddr) (((vaddr) >> 22) & 0x3ff)
82	#define PTL1_INDEX_ARCH(vaddr) 0	80	#define PTL1_INDEX_ARCH(vaddr) 0
83	#define PTL2_INDEX_ARCH(vaddr) 0	81	#define PTL2_INDEX_ARCH(vaddr) 0
84	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)	82	#define PTL3_INDEX_ARCH(vaddr) (((vaddr) >> 12) & 0x3ff)
85		83
86	/* Get PTE address accessors for each level. */	84	/* Get PTE address accessors for each level. */
87	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \	85	#define GET_PTL1_ADDRESS_ARCH(ptl0, i) \
88	(((pte_t *) (ptl0))[(i)].pfn << 12)	86	(((pte_t *) (ptl0))[(i)].pfn << 12)
89	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \	87	#define GET_PTL2_ADDRESS_ARCH(ptl1, i) \
90	(ptl1)	88	(ptl1)
91	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \	89	#define GET_PTL3_ADDRESS_ARCH(ptl2, i) \
92	(ptl2)	90	(ptl2)
93	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \	91	#define GET_FRAME_ADDRESS_ARCH(ptl3, i) \
94	(((pte_t *) (ptl3))[(i)].pfn << 12)	92	(((pte_t *) (ptl3))[(i)].pfn << 12)
95		93
96	/* Set PTE address accessors for each level. */	94	/* Set PTE address accessors for each level. */
97	#define SET_PTL0_ADDRESS_ARCH(ptl0)	95	#define SET_PTL0_ADDRESS_ARCH(ptl0)
98	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \	96	#define SET_PTL1_ADDRESS_ARCH(ptl0, i, a) \
99	(((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)	97	(((pte_t *) (ptl0))[(i)].pfn = (a) >> 12)
100	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)	98	#define SET_PTL2_ADDRESS_ARCH(ptl1, i, a)
101	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)	99	#define SET_PTL3_ADDRESS_ARCH(ptl2, i, a)
102	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \	100	#define SET_FRAME_ADDRESS_ARCH(ptl3, i, a) \
103	(((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)	101	(((pte_t *) (ptl3))[(i)].pfn = (a) >> 12)
104		102
105	/* Get PTE flags accessors for each level. */	103	/* Get PTE flags accessors for each level. */
106	#define GET_PTL1_FLAGS_ARCH(ptl0, i) \	104	#define GET_PTL1_FLAGS_ARCH(ptl0, i) \
107	get_pt_flags((pte_t *) (ptl0), (index_t) (i))	105	get_pt_flags((pte_t *) (ptl0), (index_t) (i))
108	#define GET_PTL2_FLAGS_ARCH(ptl1, i) \	106	#define GET_PTL2_FLAGS_ARCH(ptl1, i) \
109	PAGE_PRESENT	107	PAGE_PRESENT
110	#define GET_PTL3_FLAGS_ARCH(ptl2, i) \	108	#define GET_PTL3_FLAGS_ARCH(ptl2, i) \
111	PAGE_PRESENT	109	PAGE_PRESENT
112	#define GET_FRAME_FLAGS_ARCH(ptl3, i) \	110	#define GET_FRAME_FLAGS_ARCH(ptl3, i) \
113	get_pt_flags((pte_t *) (ptl3), (index_t) (i))	111	get_pt_flags((pte_t *) (ptl3), (index_t) (i))
114		112
115	/* Set PTE flags accessors for each level. */	113	/* Set PTE flags accessors for each level. */
116	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \	114	#define SET_PTL1_FLAGS_ARCH(ptl0, i, x) \
117	set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))	115	set_pt_flags((pte_t *) (ptl0), (index_t) (i), (x))
118	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)	116	#define SET_PTL2_FLAGS_ARCH(ptl1, i, x)
119	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)	117	#define SET_PTL3_FLAGS_ARCH(ptl2, i, x)
120	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \	118	#define SET_FRAME_FLAGS_ARCH(ptl3, i, x) \
121	set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))	119	set_pt_flags((pte_t *) (ptl3), (index_t) (i), (x))
122		120
123	/* Macros for querying the last-level PTEs. */	121	/* Macros for querying the last-level PTEs. */
124	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)	122	#define PTE_VALID_ARCH(pte) (((uint32_t ) (pte)) != 0)
125	#define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)	123	#define PTE_PRESENT_ARCH(pte) ((pte)->p != 0)
126	#define PTE_GET_FRAME_ARCH(pte) ((uintptr_t) ((pte)->pfn << 12))	124	#define PTE_GET_FRAME_ARCH(pte) ((uintptr_t) ((pte)->pfn << 12))
127	#define PTE_WRITABLE_ARCH(pte) 1	125	#define PTE_WRITABLE_ARCH(pte) 1
128	#define PTE_EXECUTABLE_ARCH(pte) 1	126	#define PTE_EXECUTABLE_ARCH(pte) 1
129		127
130	#ifndef __ASM__	128	#ifndef __ASM__
131		129
132	#include <mm/mm.h>	130	#include <mm/mm.h>
133	#include <arch/interrupt.h>	131	#include <arch/interrupt.h>
134		132
135	static inline int get_pt_flags(pte_t *pt, index_t i)	133	static inline int get_pt_flags(pte_t *pt, index_t i)
136	{	134	{
137	pte_t *p = &pt[i];	135	pte_t *p = &pt[i];
138		136
139	return ((1 << PAGE_CACHEABLE_SHIFT) \|	137	return ((1 << PAGE_CACHEABLE_SHIFT) \|
140	((!p->p) << PAGE_PRESENT_SHIFT) \|	138	((!p->p) << PAGE_PRESENT_SHIFT) \|
141	(1 << PAGE_USER_SHIFT) \|	139	(1 << PAGE_USER_SHIFT) \|
142	(1 << PAGE_READ_SHIFT) \|	140	(1 << PAGE_READ_SHIFT) \|
143	(1 << PAGE_WRITE_SHIFT) \|	141	(1 << PAGE_WRITE_SHIFT) \|
144	(1 << PAGE_EXEC_SHIFT) \|	142	(1 << PAGE_EXEC_SHIFT) \|
145	(p->g << PAGE_GLOBAL_SHIFT));	143	(p->g << PAGE_GLOBAL_SHIFT));
146	}	144	}
147		145
148	static inline void set_pt_flags(pte_t *pt, index_t i, int flags)	146	static inline void set_pt_flags(pte_t *pt, index_t i, int flags)
149	{	147	{
150	pte_t *p = &pt[i];	148	pte_t *p = &pt[i];
151		149
152	p->p = !(flags & PAGE_NOT_PRESENT);	150	p->p = !(flags & PAGE_NOT_PRESENT);
153	p->g = (flags & PAGE_GLOBAL) != 0;	151	p->g = (flags & PAGE_GLOBAL) != 0;
154	p->valid = 1;	152	p->valid = 1;
155	}	153	}
156		154
157	extern void page_arch_init(void);	155	extern void page_arch_init(void);
158		156
159	#define PHT_BITS 16	157	#define PHT_BITS 16
160	#define PHT_ORDER 4	158	#define PHT_ORDER 4
161		159
162	typedef struct {	160	typedef struct {
163	unsigned v : 1; /*< Valid /	161	unsigned v : 1; /*< Valid /
164	unsigned vsid : 24; /*< Virtual Segment ID /	162	unsigned vsid : 24; /*< Virtual Segment ID /
165	unsigned h : 1; /*< Primary/secondary hash /	163	unsigned h : 1; /*< Primary/secondary hash /
166	unsigned api : 6; /*< Abbreviated Page Index /	164	unsigned api : 6; /*< Abbreviated Page Index /
167	unsigned rpn : 20; /*< Real Page Number /	165	unsigned rpn : 20; /*< Real Page Number /
168	unsigned reserved0 : 3;	166	unsigned reserved0 : 3;
169	unsigned r : 1; /*< Reference /	167	unsigned r : 1; /*< Reference /
170	unsigned c : 1; /*< Change /	168	unsigned c : 1; /*< Change /
171	unsigned wimg : 4; /*< Access control /	169	unsigned wimg : 4; /*< Access control /
172	unsigned reserved1 : 1;	170	unsigned reserved1 : 1;
173	unsigned pp : 2; /*< Page protection /	171	unsigned pp : 2; /*< Page protection /
174	} phte_t;	172	} phte_t;
175		173
176	extern void pht_refill(bool data, istate_t *istate);	174	extern void pht_refill(bool data, istate_t *istate);
177	extern void pht_init(void);	175	extern void pht_init(void);
178		176
179	#endif /* __ASM__ */	177	#endif /* __ASM__ */
180		178
181	#endif /* KERNEL */	179	#endif /* KERNEL */
182		180
183	#endif	181	#endif
184		182
185	/** @}	183	/** @}
186	*/	184	*/
187		185