WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/ppc32/include/barrier.h


/*
 * Copyright (c) 2005 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32  
 * @{
 */
/** @file
 */
 
#ifndef KERN_ppc32_BARRIER_H_
#define KERN_ppc32_BARRIER_H_
 
#define CS_ENTER_BARRIER()  asm volatile ("" ::: "memory")
#define CS_LEAVE_BARRIER()  asm volatile ("" ::: "memory")
 
#define memory_barrier() asm volatile ("sync" ::: "memory")
#define read_barrier() asm volatile ("sync" ::: "memory")
#define write_barrier() asm volatile ("eieio" ::: "memory")
 
/*
 * The IMB sequence used here is valid for all possible cache models
 * on uniprocessor. SMP might require a different sequence.
 * See PowerPC Programming Environment for 32-Bit Microprocessors,
 * chapter 5.1.5.2
 */
 
static inline void smc_coherence(void *addr)
{
    asm volatile (
        "dcbst 0, %0\n"
        "sync\n"
        "icbi 0, %0\n"
        "sync\n"
        "isync\n"
        :: "r" (addr)
    );
}
 
#define COHERENCE_INVAL_MIN 4
 
static inline void smc_coherence_block(void *addr, unsigned long len)
{
    unsigned long i;
 
    for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
        asm volatile ("dcbst 0, %0\n" :: "r" (addr + i));
    }
 
    asm volatile ("sync");
 
    for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
        asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
    }
 
    asm volatile (
        "sync\n"
        "isync\n"
    );
}
 
#endif
 
/** @}
 */
 

Subversion Repositories HelenOS

(root)/branches/dynload/kernel/arch/ppc32/include/barrier.h – Rev 3153 → 4341

Rev 3153		Rev 4341
1	/*	1	/*
2	* Copyright (c) 2005 Martin Decky	2	* Copyright (c) 2005 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32	29	/** @addtogroup ppc32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ppc32_BARRIER_H_	35	#ifndef KERN_ppc32_BARRIER_H_
36	#define KERN_ppc32_BARRIER_H_	36	#define KERN_ppc32_BARRIER_H_
37		37
38	#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory")	38	#define CS_ENTER_BARRIER() asm volatile ("" ::: "memory")
39	#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory")	39	#define CS_LEAVE_BARRIER() asm volatile ("" ::: "memory")
40		40
41	#define memory_barrier() asm volatile ("sync" ::: "memory")	41	#define memory_barrier() asm volatile ("sync" ::: "memory")
42	#define read_barrier() asm volatile ("sync" ::: "memory")	42	#define read_barrier() asm volatile ("sync" ::: "memory")
43	#define write_barrier() asm volatile ("eieio" ::: "memory")	43	#define write_barrier() asm volatile ("eieio" ::: "memory")
44		44
45	/*	45	/*
46	* The IMB sequence used here is valid for all possible cache models	46	* The IMB sequence used here is valid for all possible cache models
47	* on uniprocessor. SMP might require a different sequence.	47	* on uniprocessor. SMP might require a different sequence.
48	* See PowerPC Programming Environment for 32-Bit Microprocessors,	48	* See PowerPC Programming Environment for 32-Bit Microprocessors,
49	* chapter 5.1.5.2	49	* chapter 5.1.5.2
50	*/	50	*/
51		51
52	static inline void smc_coherence(void *addr)	52	static inline void smc_coherence(void *addr)
53	{	53	{
54	asm volatile (	54	asm volatile (
55	"dcbst 0, %0\n"	55	"dcbst 0, %0\n"
56	"sync\n"	56	"sync\n"
57	"icbi 0, %0\n"	57	"icbi 0, %0\n"
-		58	"sync\n"
58	"isync\n"	59	"isync\n"
59	:: "r" (addr)	60	:: "r" (addr)
60	);	61	);
61	}	62	}
62		63
63	#define COHERENCE_INVAL_MIN 4	64	#define COHERENCE_INVAL_MIN 4
64		65
65	static inline void smc_coherence_block(void *addr, unsigned long len)	66	static inline void smc_coherence_block(void *addr, unsigned long len)
66	{	67	{
67	unsigned long i;	68	unsigned long i;
68		69
69	for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {	70	for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
70	asm volatile ("dcbst 0, %0\n" :: "r" (addr + i));	71	asm volatile ("dcbst 0, %0\n" :: "r" (addr + i));
71	}	72	}
72		73
73	asm volatile ("sync");	74	asm volatile ("sync");
74		75
75	for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {	76	for (i = 0; i < len; i += COHERENCE_INVAL_MIN) {
76	asm volatile ("icbi 0, %0\n" :: "r" (addr + i));	77	asm volatile ("icbi 0, %0\n" :: "r" (addr + i));
77	}	78	}
78		79
79	asm volatile ("isync");	80	asm volatile (
-		81	"sync\n"
-		82	"isync\n"
-		83	);
80	}	84	}
81		85
82	#endif	86	#endif
83		87
84	/** @}	88	/** @}
85	*/	89	*/
86		90