WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/ppc32/include/asm.h


/*
 * Copyright (c) 2005 Martin Decky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ppc32  
 * @{
 */
/** @file
 */
 
#ifndef KERN_ppc32_ASM_H_
#define KERN_ppc32_ASM_H_
 
#include <arch/types.h>
#include <typedefs.h>
#include <config.h>
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of EE.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_enable(void)
{
    ipl_t v;
    ipl_t tmp;
   
    asm volatile (
        "mfmsr %0\n"
        "mfmsr %1\n"
        "ori %1, %1, 1 << 15\n"
        "mtmsr %1\n"
        : "=r" (v), "=r" (tmp)
    );
    return v;
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of EE.
 *
 * @return Old interrupt priority level.
 */
static inline ipl_t interrupts_disable(void)
{
    ipl_t v;
    ipl_t tmp;
   
    asm volatile (
        "mfmsr %0\n"
        "mfmsr %1\n"
        "rlwinm %1, %1, 0, 17, 15\n"
        "mtmsr %1\n"
        : "=r" (v), "=r" (tmp)
    );
    return v;
}
 
/** Restore interrupt priority level.
 *
 * Restore EE.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl)
{
    ipl_t tmp;
   
    asm volatile (
        "mfmsr %1\n"
        "rlwimi  %0, %1, 0, 17, 15\n"
        "cmpw 0, %0, %1\n"
        "beq 0f\n"
        "mtmsr %0\n"
        "0:\n"
        : "=r" (ipl), "=r" (tmp)
        : "0" (ipl)
        : "cr0"
    );
}
 
/** Return interrupt priority level.
 *
 * Return EE.
 *
 * @return Current interrupt priority level.
 */
static inline ipl_t interrupts_read(void)
{
    ipl_t v;
   
    asm volatile (
        "mfmsr %0\n"
        : "=r" (v)
    );
    return v;
}
 
/** Return base address of current stack.
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE bytes long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uintptr_t v;
   
    asm volatile (
        "and %0, %%sp, %1\n"
        : "=r" (v)
        : "r" (~(STACK_SIZE - 1))
    );
    return v;
}
 
static inline void cpu_sleep(void)
{
}
 
void cpu_halt(void);
void asm_delay_loop(uint32_t t);
 
extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry);
 
static inline void pio_write_8(ioport8_t *port, uint8_t v)
{
    *port = v; 
}
 
static inline void pio_write_16(ioport16_t *port, uint16_t v)
{
    *port = v; 
}
 
static inline void pio_write_32(ioport32_t *port, uint32_t v)
{
    *port = v; 
}
 
static inline uint8_t pio_read_8(ioport8_t *port)
{
    return *port;
}
 
static inline uint16_t pio_read_16(ioport16_t *port)
{
    return *port;
}
 
static inline uint32_t pio_read_32(ioport32_t *port)
{
    return *port;
}
 
#endif
 
/** @}
 */
 

Rev 4344	Rev 4345
1	/*	1	/*
2	* Copyright (c) 2005 Martin Decky	2	* Copyright (c) 2005 Martin Decky
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ppc32	29	/** @addtogroup ppc32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ppc32_ASM_H_	35	#ifndef KERN_ppc32_ASM_H_
36	#define KERN_ppc32_ASM_H_	36	#define KERN_ppc32_ASM_H_
37		37
38	#include <arch/types.h>	38	#include <arch/types.h>
-		39	#include <typedefs.h>
39	#include <config.h>	40	#include <config.h>
40		41
41	/** Enable interrupts.	42	/** Enable interrupts.
42	*	43	*
43	* Enable interrupts and return previous	44	* Enable interrupts and return previous
44	* value of EE.	45	* value of EE.
45	*	46	*
46	* @return Old interrupt priority level.	47	* @return Old interrupt priority level.
47	*/	48	*/
48	static inline ipl_t interrupts_enable(void)	49	static inline ipl_t interrupts_enable(void)
49	{	50	{
50	ipl_t v;	51	ipl_t v;
51	ipl_t tmp;	52	ipl_t tmp;
52		53
53	asm volatile (	54	asm volatile (
54	"mfmsr %0\n"	55	"mfmsr %0\n"
55	"mfmsr %1\n"	56	"mfmsr %1\n"
56	"ori %1, %1, 1 << 15\n"	57	"ori %1, %1, 1 << 15\n"
57	"mtmsr %1\n"	58	"mtmsr %1\n"
58	: "=r" (v), "=r" (tmp)	59	: "=r" (v), "=r" (tmp)
59	);	60	);
60	return v;	61	return v;
61	}	62	}
62		63
63	/** Disable interrupts.	64	/** Disable interrupts.
64	*	65	*
65	* Disable interrupts and return previous	66	* Disable interrupts and return previous
66	* value of EE.	67	* value of EE.
67	*	68	*
68	* @return Old interrupt priority level.	69	* @return Old interrupt priority level.
69	*/	70	*/
70	static inline ipl_t interrupts_disable(void)	71	static inline ipl_t interrupts_disable(void)
71	{	72	{
72	ipl_t v;	73	ipl_t v;
73	ipl_t tmp;	74	ipl_t tmp;
74		75
75	asm volatile (	76	asm volatile (
76	"mfmsr %0\n"	77	"mfmsr %0\n"
77	"mfmsr %1\n"	78	"mfmsr %1\n"
78	"rlwinm %1, %1, 0, 17, 15\n"	79	"rlwinm %1, %1, 0, 17, 15\n"
79	"mtmsr %1\n"	80	"mtmsr %1\n"
80	: "=r" (v), "=r" (tmp)	81	: "=r" (v), "=r" (tmp)
81	);	82	);
82	return v;	83	return v;
83	}	84	}
84		85
85	/** Restore interrupt priority level.	86	/** Restore interrupt priority level.
86	*	87	*
87	* Restore EE.	88	* Restore EE.
88	*	89	*
89	* @param ipl Saved interrupt priority level.	90	* @param ipl Saved interrupt priority level.
90	*/	91	*/
91	static inline void interrupts_restore(ipl_t ipl)	92	static inline void interrupts_restore(ipl_t ipl)
92	{	93	{
93	ipl_t tmp;	94	ipl_t tmp;
94		95
95	asm volatile (	96	asm volatile (
96	"mfmsr %1\n"	97	"mfmsr %1\n"
97	"rlwimi %0, %1, 0, 17, 15\n"	98	"rlwimi %0, %1, 0, 17, 15\n"
98	"cmpw 0, %0, %1\n"	99	"cmpw 0, %0, %1\n"
99	"beq 0f\n"	100	"beq 0f\n"
100	"mtmsr %0\n"	101	"mtmsr %0\n"
101	"0:\n"	102	"0:\n"
102	: "=r" (ipl), "=r" (tmp)	103	: "=r" (ipl), "=r" (tmp)
103	: "0" (ipl)	104	: "0" (ipl)
104	: "cr0"	105	: "cr0"
105	);	106	);
106	}	107	}
107		108
108	/** Return interrupt priority level.	109	/** Return interrupt priority level.
109	*	110	*
110	* Return EE.	111	* Return EE.
111	*	112	*
112	* @return Current interrupt priority level.	113	* @return Current interrupt priority level.
113	*/	114	*/
114	static inline ipl_t interrupts_read(void)	115	static inline ipl_t interrupts_read(void)
115	{	116	{
116	ipl_t v;	117	ipl_t v;
117		118
118	asm volatile (	119	asm volatile (
119	"mfmsr %0\n"	120	"mfmsr %0\n"
120	: "=r" (v)	121	: "=r" (v)
121	);	122	);
122	return v;	123	return v;
123	}	124	}
124		125
125	/** Return base address of current stack.	126	/** Return base address of current stack.
126	*	127	*
127	* Return the base address of the current stack.	128	* Return the base address of the current stack.
128	* The stack is assumed to be STACK_SIZE bytes long.	129	* The stack is assumed to be STACK_SIZE bytes long.
129	* The stack must start on page boundary.	130	* The stack must start on page boundary.
130	*/	131	*/
131	static inline uintptr_t get_stack_base(void)	132	static inline uintptr_t get_stack_base(void)
132	{	133	{
133	uintptr_t v;	134	uintptr_t v;
134		135
135	asm volatile (	136	asm volatile (
136	"and %0, %%sp, %1\n"	137	"and %0, %%sp, %1\n"
137	: "=r" (v)	138	: "=r" (v)
138	: "r" (~(STACK_SIZE - 1))	139	: "r" (~(STACK_SIZE - 1))
139	);	140	);
140	return v;	141	return v;
141	}	142	}
142		143
143	static inline void cpu_sleep(void)	144	static inline void cpu_sleep(void)
144	{	145	{
145	}	146	}
146		147
147	void cpu_halt(void);	148	void cpu_halt(void);
148	void asm_delay_loop(uint32_t t);	149	void asm_delay_loop(uint32_t t);
149		150
150	extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry);	151	extern void userspace_asm(uintptr_t uspace_uarg, uintptr_t stack, uintptr_t entry);
151		152
152	static inline void pio_write_8(ioport8_t *port, uint8_t v)	153	static inline void pio_write_8(ioport8_t *port, uint8_t v)
153	{	154	{
154	*port = v;	155	*port = v;
155	}	156	}
156		157
157	static inline void pio_write_16(ioport16_t *port, uint16_t v)	158	static inline void pio_write_16(ioport16_t *port, uint16_t v)
158	{	159	{
159	*port = v;	160	*port = v;
160	}	161	}
161		162
162	static inline void pio_write_32(ioport32_t *port, uint32_t v)	163	static inline void pio_write_32(ioport32_t *port, uint32_t v)
163	{	164	{
164	*port = v;	165	*port = v;
165	}	166	}
166		167
167	static inline uint8_t pio_read_8(ioport8_t *port)	168	static inline uint8_t pio_read_8(ioport8_t *port)
168	{	169	{
169	return *port;	170	return *port;
170	}	171	}
171		172
172	static inline uint16_t pio_read_16(ioport16_t *port)	173	static inline uint16_t pio_read_16(ioport16_t *port)
173	{	174	{
174	return *port;	175	return *port;
175	}	176	}
176		177
177	static inline uint32_t pio_read_32(ioport32_t *port)	178	static inline uint32_t pio_read_32(ioport32_t *port)
178	{	179	{
179	return *port;	180	return *port;
180	}	181	}
181		182
182	#endif	183	#endif
183		184
184	/** @}	185	/** @}
185	*/	186	*/
186		187

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(root)/branches/dynload/kernel/arch/ppc32/include/asm.h – Rev 4344 → 4345