WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/mips32/src/mips32.c


/*
 * Copyright (c) 2003-2004 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup mips32
 * @{
 */
/** @file
 */
 
#include <arch.h>
#include <arch/boot.h>
#include <arch/cp0.h>
#include <arch/exception.h>
#include <mm/as.h>
 
#include <userspace.h>
#include <arch/console.h>
#include <memstr.h>
#include <proc/thread.h>
#include <proc/uarg.h>
#include <print.h>
#include <syscall/syscall.h>
#include <sysinfo/sysinfo.h>
 
#include <arch/interrupt.h>
#include <console/chardev.h>
#include <arch/barrier.h>
#include <arch/debugger.h>
#include <genarch/fb/fb.h>
#include <genarch/fb/visuals.h>
#include <macros.h>
#include <ddi/device.h>
 
#include <arch/asm/regname.h>
 
/* Size of the code jumping to the exception handler code
 * - J+NOP
 */
#define EXCEPTION_JUMP_SIZE    8
 
#define TLB_EXC ((char *) 0x80000000)
#define NORM_EXC ((char *) 0x80000180)
#define CACHE_EXC ((char *) 0x80000100)
 
 
/* Why the linker moves the variable 64K away in assembler
 * when not in .text section ????????
 */
uintptr_t supervisor_sp __attribute__ ((section (".text")));
/* Stack pointer saved when entering user mode */
/* TODO: How do we do it on SMP system???? */
bootinfo_t bootinfo __attribute__ ((section (".text")));
 
void arch_pre_main(void)
{
    /* Setup usermode */
    init.cnt = bootinfo.cnt;
   
    uint32_t i;
   
    for (i = 0; i < bootinfo.cnt; i++) {
        init.tasks[i].addr = bootinfo.tasks[i].addr;
        init.tasks[i].size = bootinfo.tasks[i].size;
    }
}
 
void arch_pre_mm_init(void)
{
    /* It is not assumed by default */
    interrupts_disable();
   
    /* Initialize dispatch table */
    exception_init();
 
    /* Copy the exception vectors to the right places */
    memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
    smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);
    memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
    smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);
    memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
    smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
   
    /*
     * Switch to BEV normal level so that exception vectors point to the
     * kernel. Clear the error level.
     */
    cp0_status_write(cp0_status_read() &
        ~(cp0_status_bev_bootstrap_bit | cp0_status_erl_error_bit));
 
    /*
     * Mask all interrupts
     */
    cp0_mask_all_int();
       
    debugger_init();
}
 
void arch_post_mm_init(void)
{
    interrupt_init();
    console_init(device_assign_devno());
#ifdef CONFIG_FB
    /* GXemul framebuffer */
    fb_properties_t gxemul_prop = {
        .addr = 0x12000000,
        .offset = 0,
        .x = 640,
        .y = 480,
        .scan = 1920,
        .visual = VISUAL_RGB_8_8_8,
    };
    fb_init(&gxemul_prop);
#endif
    sysinfo_set_item_val("machine." STRING(MACHINE), NULL, 1);
}
 
void arch_post_cpu_init(void)
{
}
 
void arch_pre_smp_init(void)
{
}
 
void arch_post_smp_init(void)
{
}
 
void userspace(uspace_arg_t *kernel_uarg)
{
    /* EXL = 1, UM = 1, IE = 1 */
    cp0_status_write(cp0_status_read() | (cp0_status_exl_exception_bit |
        cp0_status_um_bit | cp0_status_ie_enabled_bit));
    cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
    userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),
        (uintptr_t) kernel_uarg->uspace_uarg,
        (uintptr_t) kernel_uarg->uspace_entry);
   
    while (1)
        ;
}
 
/** Perform mips32 specific tasks needed before the new task is run. */
void before_task_runs_arch(void)
{
}
 
/** Perform mips32 specific tasks needed before the new thread is scheduled. */
void before_thread_runs_arch(void)
{
    supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
        SP_DELTA];
}
 
void after_thread_ran_arch(void)
{
}
 
/** Set thread-local-storage pointer
 *
 * We have it currently in K1, it is
 * possible to have it separately in the future.
 */
unative_t sys_tls_set(unative_t addr)
{
    return 0;
}
 
void arch_reboot(void)
{
    ___halt();
   
    while (1)
        ;
}
 
/** @}
 */
 

Rev 3403	Rev 3674
1	/*	1	/*
2	* Copyright (c) 2003-2004 Jakub Jermar	2	* Copyright (c) 2003-2004 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup mips32	29	/** @addtogroup mips32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#include <arch.h>	35	#include <arch.h>
36	#include <arch/boot.h>	36	#include <arch/boot.h>
37	#include <arch/cp0.h>	37	#include <arch/cp0.h>
38	#include <arch/exception.h>	38	#include <arch/exception.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40		40
41	#include <userspace.h>	41	#include <userspace.h>
42	#include <arch/console.h>	42	#include <arch/console.h>
43	#include <memstr.h>	43	#include <memstr.h>
44	#include <proc/thread.h>	44	#include <proc/thread.h>
45	#include <proc/uarg.h>	45	#include <proc/uarg.h>
46	#include <print.h>	46	#include <print.h>
47	#include <syscall/syscall.h>	47	#include <syscall/syscall.h>
48	#include <sysinfo/sysinfo.h>	48	#include <sysinfo/sysinfo.h>
49		49
50	#include <arch/interrupt.h>	50	#include <arch/interrupt.h>
51	#include <console/chardev.h>	51	#include <console/chardev.h>
52	#include <arch/barrier.h>	52	#include <arch/barrier.h>
53	#include <arch/debugger.h>	53	#include <arch/debugger.h>
54	#include <genarch/fb/fb.h>	54	#include <genarch/fb/fb.h>
55	#include <genarch/fb/visuals.h>	55	#include <genarch/fb/visuals.h>
56	#include <macros.h>	56	#include <macros.h>
57	#include <ddi/device.h>	57	#include <ddi/device.h>
58		58
59	#include <arch/asm/regname.h>	59	#include <arch/asm/regname.h>
60		60
61	/* Size of the code jumping to the exception handler code	61	/* Size of the code jumping to the exception handler code
62	* - J+NOP	62	* - J+NOP
63	*/	63	*/
64	#define EXCEPTION_JUMP_SIZE 8	64	#define EXCEPTION_JUMP_SIZE 8
65		65
66	#define TLB_EXC ((char *) 0x80000000)	66	#define TLB_EXC ((char *) 0x80000000)
67	#define NORM_EXC ((char *) 0x80000180)	67	#define NORM_EXC ((char *) 0x80000180)
68	#define CACHE_EXC ((char *) 0x80000100)	68	#define CACHE_EXC ((char *) 0x80000100)
69		69
70		70
71	/* Why the linker moves the variable 64K away in assembler	71	/* Why the linker moves the variable 64K away in assembler
72	* when not in .text section ????????	72	* when not in .text section ????????
73	*/	73	*/
74	uintptr_t supervisor_sp __attribute__ ((section (".text")));	74	uintptr_t supervisor_sp __attribute__ ((section (".text")));
75	/* Stack pointer saved when entering user mode */	75	/* Stack pointer saved when entering user mode */
76	/* TODO: How do we do it on SMP system???? */	76	/* TODO: How do we do it on SMP system???? */
77	bootinfo_t bootinfo __attribute__ ((section (".text")));	77	bootinfo_t bootinfo __attribute__ ((section (".text")));
78		78
79	void arch_pre_main(void)	79	void arch_pre_main(void)
80	{	80	{
81	/* Setup usermode */	81	/* Setup usermode */
82	init.cnt = bootinfo.cnt;	82	init.cnt = bootinfo.cnt;
83		83
84	uint32_t i;	84	uint32_t i;
85		85
86	for (i = 0; i < bootinfo.cnt; i++) {	86	for (i = 0; i < bootinfo.cnt; i++) {
87	init.tasks[i].addr = bootinfo.tasks[i].addr;	87	init.tasks[i].addr = bootinfo.tasks[i].addr;
88	init.tasks[i].size = bootinfo.tasks[i].size;	88	init.tasks[i].size = bootinfo.tasks[i].size;
89	}	89	}
90	}	90	}
91		91
92	void arch_pre_mm_init(void)	92	void arch_pre_mm_init(void)
93	{	93	{
94	/* It is not assumed by default */	94	/* It is not assumed by default */
95	interrupts_disable();	95	interrupts_disable();
96		96
97	/* Initialize dispatch table */	97	/* Initialize dispatch table */
98	exception_init();	98	exception_init();
99		99
100	/* Copy the exception vectors to the right places */	100	/* Copy the exception vectors to the right places */
101	memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);	101	memcpy(TLB_EXC, (char *) tlb_refill_entry, EXCEPTION_JUMP_SIZE);
102	smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);	102	smc_coherence_block(TLB_EXC, EXCEPTION_JUMP_SIZE);
103	memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);	103	memcpy(NORM_EXC, (char *) exception_entry, EXCEPTION_JUMP_SIZE);
104	smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);	104	smc_coherence_block(NORM_EXC, EXCEPTION_JUMP_SIZE);
105	memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);	105	memcpy(CACHE_EXC, (char *) cache_error_entry, EXCEPTION_JUMP_SIZE);
106	smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);	106	smc_coherence_block(CACHE_EXC, EXCEPTION_JUMP_SIZE);
107		107
108	/*	108	/*
109	* Switch to BEV normal level so that exception vectors point to the	109	* Switch to BEV normal level so that exception vectors point to the
110	* kernel. Clear the error level.	110	* kernel. Clear the error level.
111	*/	111	*/
112	cp0_status_write(cp0_status_read() &	112	cp0_status_write(cp0_status_read() &
113	~(cp0_status_bev_bootstrap_bit \| cp0_status_erl_error_bit));	113	~(cp0_status_bev_bootstrap_bit \| cp0_status_erl_error_bit));
114		114
115	/*	115	/*
116	* Mask all interrupts	116	* Mask all interrupts
117	*/	117	*/
118	cp0_mask_all_int();	118	cp0_mask_all_int();
119		119
120	debugger_init();	120	debugger_init();
121	}	121	}
122		122
123	void arch_post_mm_init(void)	123	void arch_post_mm_init(void)
124	{	124	{
125	interrupt_init();	125	interrupt_init();
126	console_init(device_assign_devno());	126	console_init(device_assign_devno());
127	#ifdef CONFIG_FB	127	#ifdef CONFIG_FB
128	/* GXemul framebuffer */	128	/* GXemul framebuffer */
-		129	fb_properties_t gxemul_prop = {
-		130	.addr = 0x12000000,
-		131	.offset = 0,
-		132	.x = 640,
-		133	.y = 480,
-		134	.scan = 1920,
129	fb_init(0x12000000, 640, 480, 1920, VISUAL_RGB_8_8_8);	135	.visual = VISUAL_RGB_8_8_8,
-		136	};
-		137	fb_init(&gxemul_prop);
130	#endif	138	#endif
131	sysinfo_set_item_val("machine." STRING(MACHINE), NULL, 1);	139	sysinfo_set_item_val("machine." STRING(MACHINE), NULL, 1);
132	}	140	}
133		141
134	void arch_post_cpu_init(void)	142	void arch_post_cpu_init(void)
135	{	143	{
136	}	144	}
137		145
138	void arch_pre_smp_init(void)	146	void arch_pre_smp_init(void)
139	{	147	{
140	}	148	}
141		149
142	void arch_post_smp_init(void)	150	void arch_post_smp_init(void)
143	{	151	{
144	}	152	}
145		153
146	void userspace(uspace_arg_t *kernel_uarg)	154	void userspace(uspace_arg_t *kernel_uarg)
147	{	155	{
148	/* EXL = 1, UM = 1, IE = 1 */	156	/* EXL = 1, UM = 1, IE = 1 */
149	cp0_status_write(cp0_status_read() \| (cp0_status_exl_exception_bit \|	157	cp0_status_write(cp0_status_read() \| (cp0_status_exl_exception_bit \|
150	cp0_status_um_bit \| cp0_status_ie_enabled_bit));	158	cp0_status_um_bit \| cp0_status_ie_enabled_bit));
151	cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);	159	cp0_epc_write((uintptr_t) kernel_uarg->uspace_entry);
152	userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),	160	userspace_asm(((uintptr_t) kernel_uarg->uspace_stack + PAGE_SIZE),
153	(uintptr_t) kernel_uarg->uspace_uarg,	161	(uintptr_t) kernel_uarg->uspace_uarg,
154	(uintptr_t) kernel_uarg->uspace_entry);	162	(uintptr_t) kernel_uarg->uspace_entry);
155		163
156	while (1)	164	while (1)
157	;	165	;
158	}	166	}
159		167
160	/** Perform mips32 specific tasks needed before the new task is run. */	168	/** Perform mips32 specific tasks needed before the new task is run. */
161	void before_task_runs_arch(void)	169	void before_task_runs_arch(void)
162	{	170	{
163	}	171	}
164		172
165	/** Perform mips32 specific tasks needed before the new thread is scheduled. */	173	/** Perform mips32 specific tasks needed before the new thread is scheduled. */
166	void before_thread_runs_arch(void)	174	void before_thread_runs_arch(void)
167	{	175	{
168	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -	176	supervisor_sp = (uintptr_t) &THREAD->kstack[THREAD_STACK_SIZE -
169	SP_DELTA];	177	SP_DELTA];
170	}	178	}
171		179
172	void after_thread_ran_arch(void)	180	void after_thread_ran_arch(void)
173	{	181	{
174	}	182	}
175		183
176	/** Set thread-local-storage pointer	184	/** Set thread-local-storage pointer
177	*	185	*
178	* We have it currently in K1, it is	186	* We have it currently in K1, it is
179	* possible to have it separately in the future.	187	* possible to have it separately in the future.
180	*/	188	*/
181	unative_t sys_tls_set(unative_t addr)	189	unative_t sys_tls_set(unative_t addr)
182	{	190	{
183	return 0;	191	return 0;
184	}	192	}
185		193
186	void arch_reboot(void)	194	void arch_reboot(void)
187	{	195	{
188	___halt();	196	___halt();
189		197
190	while (1)	198	while (1)
191	;	199	;
192	}	200	}
193		201
194	/** @}	202	/** @}
195	*/	203	*/
196		204

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(root)/branches/dynload/kernel/arch/mips32/src/mips32.c – Rev 3403 → 3674