WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/ia64/include/mm/page.h


/*
 * Copyright (c) 2005 - 2006 Jakub Jermar
 * Copyright (c) 2006 Jakub Vana
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia64mm 
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia64_PAGE_H_
#define KERN_ia64_PAGE_H_
 
#include <arch/mm/frame.h>
 
#define PAGE_SIZE   FRAME_SIZE
#define PAGE_WIDTH  FRAME_WIDTH
 
#ifdef KERNEL
 
/** Bit width of the TLB-locked portion of kernel address space. */
#define KERNEL_PAGE_WIDTH       28  /* 256M */
#define IO_PAGE_WIDTH           26  /* 64M */
#define FW_PAGE_WIDTH           28  /* 256M */
 
#define USPACE_IO_PAGE_WIDTH        12  /* 4K */
 
 
/*
 * Statically mapped IO spaces - offsets to 0xe...00 of virtual addresses
 * because of "minimal virtual bits implemented is 51" it is possible to
 * have values up to 0x0007000000000000
 */
 
/* Firmware area (bellow 4GB in phys mem) */
#define FW_OFFSET             0x00000000F0000000
/* Legacy IO space */
#define IO_OFFSET             0x0001000000000000
/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */
#define VIO_OFFSET            0x0002000000000000
 
 
 
 
#define PPN_SHIFT           12
 
#define VRN_SHIFT           61
#define VRN_MASK            (7LL << VRN_SHIFT)
#define VA2VRN(va)          ((va)>>VRN_SHIFT)
 
#ifdef __ASM__
#define VRN_KERNEL          7
#else
#define VRN_KERNEL          7LL
#endif
 
#define REGION_REGISTERS        8
 
#define KA2PA(x)    ((uintptr_t) (x - (VRN_KERNEL << VRN_SHIFT)))
#define PA2KA(x)    ((uintptr_t) (x + (VRN_KERNEL << VRN_SHIFT)))
 
#define VHPT_WIDTH          20  /* 1M */
#define VHPT_SIZE           (1 << VHPT_WIDTH)
 
#define PTA_BASE_SHIFT          15
 
/** Memory Attributes. */
#define MA_WRITEBACK    0x0
#define MA_UNCACHEABLE  0x4
 
/** Privilege Levels. Only the most and the least privileged ones are ever used. */
#define PL_KERNEL   0x0
#define PL_USER     0x3
 
/* Access Rigths. Only certain combinations are used by the kernel. */
#define AR_READ     0x0
#define AR_EXECUTE  0x1
#define AR_WRITE    0x2
 
#ifndef __ASM__
 
#include <arch/mm/as.h>
#include <arch/mm/frame.h>
#include <arch/interrupt.h>
#include <arch/barrier.h>
#include <arch/mm/asid.h>
#include <arch/types.h>
#include <debug.h>
 
struct vhpt_tag_info {
    unsigned long long tag : 63;
    unsigned ti : 1;
} __attribute__ ((packed));
 
union vhpt_tag {
    struct vhpt_tag_info tag_info;
    unsigned tag_word;
};
 
struct vhpt_entry_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned : 1;
    unsigned ma : 3;
    unsigned a : 1;
    unsigned d : 1;
    unsigned pl : 2;
    unsigned ar : 3;
    unsigned long long ppn : 38;
    unsigned : 2;
    unsigned ed : 1;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned key : 24;
    unsigned : 32;
   
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    uint64_t ig3 : 64;
} __attribute__ ((packed));
 
struct vhpt_entry_not_present {
    /* Word 0 */
    unsigned p : 1;
    unsigned long long ig0 : 52;
    unsigned ig1 : 11;
   
    /* Word 1 */
    unsigned : 2;
    unsigned ps : 6;
    unsigned long long ig2 : 56;
 
    /* Word 2 */
    union vhpt_tag tag;
   
    /* Word 3 */                                                   
    uint64_t ig3 : 64;
} __attribute__ ((packed));
 
typedef union vhpt_entry {
    struct vhpt_entry_present present;
    struct vhpt_entry_not_present not_present;
    uint64_t word[4];
} vhpt_entry_t;
 
struct region_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned ps : 6;
    unsigned rid : 24;
    unsigned : 32;
} __attribute__ ((packed));
 
typedef union region_register {
    struct region_register_map map;
    unsigned long long word;
} region_register;
 
struct pta_register_map {
    unsigned ve : 1;
    unsigned : 1;
    unsigned size : 6;
    unsigned vf : 1;
    unsigned : 6;
    unsigned long long base : 49;
} __attribute__ ((packed));
 
typedef union pta_register {
    struct pta_register_map map;
    uint64_t word;
} pta_register;
 
/** Return Translation Hashed Entry Address.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return Address of the head of VHPT collision chain.
 */
static inline uint64_t thash(uint64_t va)
{
    uint64_t ret;
 
    asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Return Translation Hashed Entry Tag.
 *
 * VRN bits are used to read RID (ASID) from one
 * of the eight region registers.
 *
 * @param va Virtual address including VRN bits.
 *
 * @return The unique tag for VPN and RID in the collision chain returned by thash().
 */
static inline uint64_t ttag(uint64_t va)
{
    uint64_t ret;
 
    asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
 
    return ret;
}
 
/** Read Region Register.
 *
 * @param i Region register index.
 *
 * @return Current contents of rr[i].
 */
static inline uint64_t rr_read(index_t i)
{
    uint64_t ret;
    ASSERT(i < REGION_REGISTERS);
    asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
    return ret;
}
 
/** Write Region Register.
 *
 * @param i Region register index.
 * @param v Value to be written to rr[i].
 */
static inline void rr_write(index_t i, uint64_t v)
{
    ASSERT(i < REGION_REGISTERS);
    asm volatile (
        "mov rr[%0] = %1\n"
        :
        : "r" (i << VRN_SHIFT), "r" (v)
    );
}
 
/** Read Page Table Register.
 *
 * @return Current value stored in PTA.
 */
static inline uint64_t pta_read(void)
{
    uint64_t ret;
   
    asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
   
    return ret;
}
 
/** Write Page Table Register.
 *
 * @param v New value to be stored in PTA.
 */
static inline void pta_write(uint64_t v)
{
    asm volatile ("mov cr.pta = %0\n" : : "r" (v));
}
 
extern void page_arch_init(void);
 
extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);
extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);
extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);
 
#endif /* __ASM__ */
 
#endif /* KERNEL */
 
#endif
 
/** @}
 */
 

Rev 3674	Rev 4338
1	/*	1	/*
2	* Copyright (c) 2005 - 2006 Jakub Jermar	2	* Copyright (c) 2005 - 2006 Jakub Jermar
3	* Copyright (c) 2006 Jakub Vana	3	* Copyright (c) 2006 Jakub Vana
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	/** @addtogroup ia64mm	30	/** @addtogroup ia64mm
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36	#ifndef KERN_ia64_PAGE_H_	36	#ifndef KERN_ia64_PAGE_H_
37	#define KERN_ia64_PAGE_H_	37	#define KERN_ia64_PAGE_H_
38		38
39	#include <arch/mm/frame.h>	39	#include <arch/mm/frame.h>
40		40
41	#define PAGE_SIZE FRAME_SIZE	41	#define PAGE_SIZE FRAME_SIZE
42	#define PAGE_WIDTH FRAME_WIDTH	42	#define PAGE_WIDTH FRAME_WIDTH
43		43
44	#ifdef KERNEL	44	#ifdef KERNEL
45		45
46	/** Bit width of the TLB-locked portion of kernel address space. */	46	/** Bit width of the TLB-locked portion of kernel address space. */
47	#define KERNEL_PAGE_WIDTH 28 /* 256M */	47	#define KERNEL_PAGE_WIDTH 28 /* 256M */
48	#define IO_PAGE_WIDTH 26 /* 64M */	48	#define IO_PAGE_WIDTH 26 /* 64M */
49	#define FW_PAGE_WIDTH 28 /* 256M */	49	#define FW_PAGE_WIDTH 28 /* 256M */
50		50
51	#define USPACE_IO_PAGE_WIDTH 12 /* 4K */	51	#define USPACE_IO_PAGE_WIDTH 12 /* 4K */
52		52
53		53
54		54	/*
55	/** Staticly mapped IO spaces - offsets to 0xe...00 of virtual adresses	55	* Statically mapped IO spaces - offsets to 0xe...00 of virtual addresses
56	becauce of "minimal virtual bits implemented is 51"	56	* because of "minimal virtual bits implemented is 51" it is possible to
57	it is possible to have here values up to 0x0007000000000000	57	* have values up to 0x0007000000000000
58	*/	58	*/
59		59
60	/* Firmware area (bellow 4GB in phys mem) */	60	/* Firmware area (bellow 4GB in phys mem) */
61	#define FW_OFFSET 0x00000000F0000000	61	#define FW_OFFSET 0x00000000F0000000
62	/* Legacy IO space */	62	/* Legacy IO space */
63	#define IO_OFFSET 0x0001000000000000	63	#define IO_OFFSET 0x0001000000000000
64	/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000*/	64	/* Videoram - now mapped to 0 as VGA text mode vram on 0xb8000 */
65	#define VIO_OFFSET 0x0002000000000000	65	#define VIO_OFFSET 0x0002000000000000
66		66
67		67
68		-
69		-
70	#define PPN_SHIFT 12	68	#define PPN_SHIFT 12
71		69
72	#define VRN_SHIFT 61	70	#define VRN_SHIFT 61
73	#define VRN_MASK (7LL << VRN_SHIFT)	71	#define VRN_MASK (7LL << VRN_SHIFT)
74	#define VA2VRN(va) ((va)>>VRN_SHIFT)	72	#define VA2VRN(va) ((va)>>VRN_SHIFT)
75		73
76	#ifdef __ASM__	74	#ifdef __ASM__
77	#define VRN_KERNEL 7	75	#define VRN_KERNEL 7
78	#else	76	#else
79	#define VRN_KERNEL 7LL	77	#define VRN_KERNEL 7LL
80	#endif	78	#endif
81		79
82	#define REGION_REGISTERS 8	80	#define REGION_REGISTERS 8
83		81
84	#define KA2PA(x) ((uintptr_t) (x-(VRN_KERNEL<<VRN_SHIFT)))	82	#define KA2PA(x) ((uintptr_t) (x - (VRN_KERNEL << VRN_SHIFT)))
85	#define PA2KA(x) ((uintptr_t) (x+(VRN_KERNEL<<VRN_SHIFT)))	83	#define PA2KA(x) ((uintptr_t) (x + (VRN_KERNEL << VRN_SHIFT)))
86		84
87	#define VHPT_WIDTH 20 /* 1M */	85	#define VHPT_WIDTH 20 /* 1M */
88	#define VHPT_SIZE (1 << VHPT_WIDTH)	86	#define VHPT_SIZE (1 << VHPT_WIDTH)
89		87
90	#define PTA_BASE_SHIFT 15	88	#define PTA_BASE_SHIFT 15
91		89
92	/** Memory Attributes. */	90	/** Memory Attributes. */
93	#define MA_WRITEBACK 0x0	91	#define MA_WRITEBACK 0x0
94	#define MA_UNCACHEABLE 0x4	92	#define MA_UNCACHEABLE 0x4
95		93
96	/** Privilege Levels. Only the most and the least privileged ones are ever used. */	94	/** Privilege Levels. Only the most and the least privileged ones are ever used. */
97	#define PL_KERNEL 0x0	95	#define PL_KERNEL 0x0
98	#define PL_USER 0x3	96	#define PL_USER 0x3
99		97
100	/* Access Rigths. Only certain combinations are used by the kernel. */	98	/* Access Rigths. Only certain combinations are used by the kernel. */
101	#define AR_READ 0x0	99	#define AR_READ 0x0
102	#define AR_EXECUTE 0x1	100	#define AR_EXECUTE 0x1
103	#define AR_WRITE 0x2	101	#define AR_WRITE 0x2
104		102
105	#ifndef __ASM__	103	#ifndef __ASM__
106		104
107	#include <arch/mm/as.h>	105	#include <arch/mm/as.h>
108	#include <arch/mm/frame.h>	106	#include <arch/mm/frame.h>
109	#include <arch/interrupt.h>	107	#include <arch/interrupt.h>
110	#include <arch/barrier.h>	108	#include <arch/barrier.h>
111	#include <arch/mm/asid.h>	109	#include <arch/mm/asid.h>
112	#include <arch/types.h>	110	#include <arch/types.h>
113	#include <debug.h>	111	#include <debug.h>
114		112
115	struct vhpt_tag_info {	113	struct vhpt_tag_info {
116	unsigned long long tag : 63;	114	unsigned long long tag : 63;
117	unsigned ti : 1;	115	unsigned ti : 1;
118	} __attribute__ ((packed));	116	} __attribute__ ((packed));
119		117
120	union vhpt_tag {	118	union vhpt_tag {
121	struct vhpt_tag_info tag_info;	119	struct vhpt_tag_info tag_info;
122	unsigned tag_word;	120	unsigned tag_word;
123	};	121	};
124		122
125	struct vhpt_entry_present {	123	struct vhpt_entry_present {
126	/* Word 0 */	124	/* Word 0 */
127	unsigned p : 1;	125	unsigned p : 1;
128	unsigned : 1;	126	unsigned : 1;
129	unsigned ma : 3;	127	unsigned ma : 3;
130	unsigned a : 1;	128	unsigned a : 1;
131	unsigned d : 1;	129	unsigned d : 1;
132	unsigned pl : 2;	130	unsigned pl : 2;
133	unsigned ar : 3;	131	unsigned ar : 3;
134	unsigned long long ppn : 38;	132	unsigned long long ppn : 38;
135	unsigned : 2;	133	unsigned : 2;
136	unsigned ed : 1;	134	unsigned ed : 1;
137	unsigned ig1 : 11;	135	unsigned ig1 : 11;
138		136
139	/* Word 1 */	137	/* Word 1 */
140	unsigned : 2;	138	unsigned : 2;
141	unsigned ps : 6;	139	unsigned ps : 6;
142	unsigned key : 24;	140	unsigned key : 24;
143	unsigned : 32;	141	unsigned : 32;
144		142
145	/* Word 2 */	143	/* Word 2 */
146	union vhpt_tag tag;	144	union vhpt_tag tag;
147		145
148	/* Word 3 */	146	/* Word 3 */
149	uint64_t ig3 : 64;	147	uint64_t ig3 : 64;
150	} __attribute__ ((packed));	148	} __attribute__ ((packed));
151		149
152	struct vhpt_entry_not_present {	150	struct vhpt_entry_not_present {
153	/* Word 0 */	151	/* Word 0 */
154	unsigned p : 1;	152	unsigned p : 1;
155	unsigned long long ig0 : 52;	153	unsigned long long ig0 : 52;
156	unsigned ig1 : 11;	154	unsigned ig1 : 11;
157		155
158	/* Word 1 */	156	/* Word 1 */
159	unsigned : 2;	157	unsigned : 2;
160	unsigned ps : 6;	158	unsigned ps : 6;
161	unsigned long long ig2 : 56;	159	unsigned long long ig2 : 56;
162		160
163	/* Word 2 */	161	/* Word 2 */
164	union vhpt_tag tag;	162	union vhpt_tag tag;
165		163
166	/* Word 3 */	164	/* Word 3 */
167	uint64_t ig3 : 64;	165	uint64_t ig3 : 64;
168	} __attribute__ ((packed));	166	} __attribute__ ((packed));
169		167
170	typedef union vhpt_entry {	168	typedef union vhpt_entry {
171	struct vhpt_entry_present present;	169	struct vhpt_entry_present present;
172	struct vhpt_entry_not_present not_present;	170	struct vhpt_entry_not_present not_present;
173	uint64_t word[4];	171	uint64_t word[4];
174	} vhpt_entry_t;	172	} vhpt_entry_t;
175		173
176	struct region_register_map {	174	struct region_register_map {
177	unsigned ve : 1;	175	unsigned ve : 1;
178	unsigned : 1;	176	unsigned : 1;
179	unsigned ps : 6;	177	unsigned ps : 6;
180	unsigned rid : 24;	178	unsigned rid : 24;
181	unsigned : 32;	179	unsigned : 32;
182	} __attribute__ ((packed));	180	} __attribute__ ((packed));
183		181
184	typedef union region_register {	182	typedef union region_register {
185	struct region_register_map map;	183	struct region_register_map map;
186	unsigned long long word;	184	unsigned long long word;
187	} region_register;	185	} region_register;
188		186
189	struct pta_register_map {	187	struct pta_register_map {
190	unsigned ve : 1;	188	unsigned ve : 1;
191	unsigned : 1;	189	unsigned : 1;
192	unsigned size : 6;	190	unsigned size : 6;
193	unsigned vf : 1;	191	unsigned vf : 1;
194	unsigned : 6;	192	unsigned : 6;
195	unsigned long long base : 49;	193	unsigned long long base : 49;
196	} __attribute__ ((packed));	194	} __attribute__ ((packed));
197		195
198	typedef union pta_register {	196	typedef union pta_register {
199	struct pta_register_map map;	197	struct pta_register_map map;
200	uint64_t word;	198	uint64_t word;
201	} pta_register;	199	} pta_register;
202		200
203	/** Return Translation Hashed Entry Address.	201	/** Return Translation Hashed Entry Address.
204	*	202	*
205	* VRN bits are used to read RID (ASID) from one	203	* VRN bits are used to read RID (ASID) from one
206	* of the eight region registers registers.	204	* of the eight region registers registers.
207	*	205	*
208	* @param va Virtual address including VRN bits.	206	* @param va Virtual address including VRN bits.
209	*	207	*
210	* @return Address of the head of VHPT collision chain.	208	* @return Address of the head of VHPT collision chain.
211	*/	209	*/
212	static inline uint64_t thash(uint64_t va)	210	static inline uint64_t thash(uint64_t va)
213	{	211	{
214	uint64_t ret;	212	uint64_t ret;
215		213
216	asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));	214	asm volatile ("thash %0 = %1\n" : "=r" (ret) : "r" (va));
217		215
218	return ret;	216	return ret;
219	}	217	}
220		218
221	/** Return Translation Hashed Entry Tag.	219	/** Return Translation Hashed Entry Tag.
222	*	220	*
223	* VRN bits are used to read RID (ASID) from one	221	* VRN bits are used to read RID (ASID) from one
224	* of the eight region registers.	222	* of the eight region registers.
225	*	223	*
226	* @param va Virtual address including VRN bits.	224	* @param va Virtual address including VRN bits.
227	*	225	*
228	* @return The unique tag for VPN and RID in the collision chain returned by thash().	226	* @return The unique tag for VPN and RID in the collision chain returned by thash().
229	*/	227	*/
230	static inline uint64_t ttag(uint64_t va)	228	static inline uint64_t ttag(uint64_t va)
231	{	229	{
232	uint64_t ret;	230	uint64_t ret;
233		231
234	asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));	232	asm volatile ("ttag %0 = %1\n" : "=r" (ret) : "r" (va));
235		233
236	return ret;	234	return ret;
237	}	235	}
238		236
239	/** Read Region Register.	237	/** Read Region Register.
240	*	238	*
241	* @param i Region register index.	239	* @param i Region register index.
242	*	240	*
243	* @return Current contents of rr[i].	241	* @return Current contents of rr[i].
244	*/	242	*/
245	static inline uint64_t rr_read(index_t i)	243	static inline uint64_t rr_read(index_t i)
246	{	244	{
247	uint64_t ret;	245	uint64_t ret;
248	ASSERT(i < REGION_REGISTERS);	246	ASSERT(i < REGION_REGISTERS);
249	asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));	247	asm volatile ("mov %0 = rr[%1]\n" : "=r" (ret) : "r" (i << VRN_SHIFT));
250	return ret;	248	return ret;
251	}	249	}
252		250
253	/** Write Region Register.	251	/** Write Region Register.
254	*	252	*
255	* @param i Region register index.	253	* @param i Region register index.
256	* @param v Value to be written to rr[i].	254	* @param v Value to be written to rr[i].
257	*/	255	*/
258	static inline void rr_write(index_t i, uint64_t v)	256	static inline void rr_write(index_t i, uint64_t v)
259	{	257	{
260	ASSERT(i < REGION_REGISTERS);	258	ASSERT(i < REGION_REGISTERS);
261	asm volatile (	259	asm volatile (
262	"mov rr[%0] = %1\n"	260	"mov rr[%0] = %1\n"
263	:	261	:
264	: "r" (i << VRN_SHIFT), "r" (v)	262	: "r" (i << VRN_SHIFT), "r" (v)
265	);	263	);
266	}	264	}
267		265
268	/** Read Page Table Register.	266	/** Read Page Table Register.
269	*	267	*
270	* @return Current value stored in PTA.	268	* @return Current value stored in PTA.
271	*/	269	*/
272	static inline uint64_t pta_read(void)	270	static inline uint64_t pta_read(void)
273	{	271	{
274	uint64_t ret;	272	uint64_t ret;
275		273
276	asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));	274	asm volatile ("mov %0 = cr.pta\n" : "=r" (ret));
277		275
278	return ret;	276	return ret;
279	}	277	}
280		278
281	/** Write Page Table Register.	279	/** Write Page Table Register.
282	*	280	*
283	* @param v New value to be stored in PTA.	281	* @param v New value to be stored in PTA.
284	*/	282	*/
285	static inline void pta_write(uint64_t v)	283	static inline void pta_write(uint64_t v)
286	{	284	{
287	asm volatile ("mov cr.pta = %0\n" : : "r" (v));	285	asm volatile ("mov cr.pta = %0\n" : : "r" (v));
288	}	286	}
289		287
290	extern void page_arch_init(void);	288	extern void page_arch_init(void);
291		289
292	extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);	290	extern vhpt_entry_t *vhpt_hash(uintptr_t page, asid_t asid);
293	extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);	291	extern bool vhpt_compare(uintptr_t page, asid_t asid, vhpt_entry_t *v);
294	extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);	292	extern void vhpt_set_record(vhpt_entry_t *v, uintptr_t page, asid_t asid, uintptr_t frame, int flags);
295		293
296	#endif /* __ASM__ */	294	#endif /* __ASM__ */
297		295
298	#endif /* KERNEL */	296	#endif /* KERNEL */
299		297
300	#endif	298	#endif
301		299
302	/** @}	300	/** @}
303	*/	301	*/
304		302

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(root)/branches/dynload/kernel/arch/ia64/include/mm/page.h – Rev 3674 → 4338