WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/ia64/include/interrupt.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia64interrupt
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia64_INTERRUPT_H_
#define KERN_ia64_INTERRUPT_H_
 
#include <arch/types.h>
#include <arch/register.h>
 
/** ia64 has 256 INRs. */
#define INR_COUNT   256
 
/*
 * We need to keep this just to compile.
 * We might eventually move interrupt/ stuff
 * to genarch.
 */
#define IVT_ITEMS       0
#define IVT_FIRST       0
 
/** External Interrupt vectors. */
 
#define VECTOR_TLB_SHOOTDOWN_IPI 0xf0
#define INTERRUPT_TIMER     255
#define IRQ_KBD         (0x01+LAGACY_INTERRUPT_BASE)
#define IRQ_MOUSE       (0x0c+LAGACY_INTERRUPT_BASE)
#define INTERRUPT_SPURIOUS  15
#define LAGACY_INTERRUPT_BASE   0x20
 
/** General Exception codes. */
#define GE_ILLEGALOP        0
#define GE_PRIVOP       1
#define GE_PRIVREG      2
#define GE_RESREGFLD        3
#define GE_DISBLDISTRAN     4
#define GE_ILLEGALDEP       8
 
#define EOI 0       /**< The actual value doesn't matter. */
 
typedef struct {
    uint128_t f2;
    uint128_t f3;
    uint128_t f4;
    uint128_t f5;
    uint128_t f6;
    uint128_t f7;
    uint128_t f8;
    uint128_t f9;
    uint128_t f10;
    uint128_t f11;
    uint128_t f12;
    uint128_t f13;
    uint128_t f14;
    uint128_t f15;
    uint128_t f16;
    uint128_t f17;
    uint128_t f18;
    uint128_t f19;
    uint128_t f20;
    uint128_t f21;
    uint128_t f22;
    uint128_t f23;
    uint128_t f24;
    uint128_t f25;
    uint128_t f26;
    uint128_t f27;
    uint128_t f28;
    uint128_t f29;
    uint128_t f30;
    uint128_t f31;
       
    uintptr_t ar_bsp;
    uintptr_t ar_bspstore;
    uintptr_t ar_bspstore_new;
    uint64_t ar_rnat;
    uint64_t ar_ifs;
    uint64_t ar_pfs;
    uint64_t ar_rsc;
    uintptr_t cr_ifa;
    cr_isr_t cr_isr;
    uintptr_t cr_iipa;
    psr_t cr_ipsr;
    uintptr_t cr_iip;
    uint64_t pr;
    uintptr_t sp;
   
    /*
     * The following variables are defined only for break_instruction
     * handler.
     */
    uint64_t in0;
    uint64_t in1;
    uint64_t in2;
    uint64_t in3;
    uint64_t in4;
    uint64_t in5;
    uint64_t in6;
} istate_t;
 
static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
{
    istate->cr_iip = retaddr;
    istate->cr_ipsr.ri = 0;     /* return to instruction slot #0 */
}
 
static inline unative_t istate_get_pc(istate_t *istate)
{
    return istate->cr_iip;
}
 
static inline int istate_from_uspace(istate_t *istate)
{
    return (istate->cr_iip) < 0xe000000000000000ULL;
}
 
extern void *ivt;
 
extern void general_exception(uint64_t vector, istate_t *istate);
extern int break_instruction(uint64_t vector, istate_t *istate);
extern void universal_handler(uint64_t vector, istate_t *istate);
extern void nop_handler(uint64_t vector, istate_t *istate);
extern void external_interrupt(uint64_t vector, istate_t *istate);
extern void disabled_fp_register(uint64_t vector, istate_t *istate);
 
 
#endif
 
/** @}
 */
 

Rev 2927	Rev 3674
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia64interrupt	29	/** @addtogroup ia64interrupt
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ia64_INTERRUPT_H_	35	#ifndef KERN_ia64_INTERRUPT_H_
36	#define KERN_ia64_INTERRUPT_H_	36	#define KERN_ia64_INTERRUPT_H_
37		37
38	#include <arch/types.h>	38	#include <arch/types.h>
39	#include <arch/register.h>	39	#include <arch/register.h>
40		40
41	/** ia64 has 256 INRs. */	41	/** ia64 has 256 INRs. */
42	#define INR_COUNT 256	42	#define INR_COUNT 256
43		43
44	/*	44	/*
45	* We need to keep this just to compile.	45	* We need to keep this just to compile.
46	* We might eventually move interrupt/ stuff	46	* We might eventually move interrupt/ stuff
47	* to genarch.	47	* to genarch.
48	*/	48	*/
49	#define IVT_ITEMS 0	49	#define IVT_ITEMS 0
50	#define IVT_FIRST 0	50	#define IVT_FIRST 0
51		51
52	/** External Interrupt vectors. */	52	/** External Interrupt vectors. */
-		53
-		54	#define VECTOR_TLB_SHOOTDOWN_IPI 0xf0
53	#define INTERRUPT_TIMER 255	55	#define INTERRUPT_TIMER 255
54	#define IRQ_KBD 241	56	#define IRQ_KBD (0x01+LAGACY_INTERRUPT_BASE)
55	#define IRQ_MOUSE 252	57	#define IRQ_MOUSE (0x0c+LAGACY_INTERRUPT_BASE)
56	#define INTERRUPT_SPURIOUS 15	58	#define INTERRUPT_SPURIOUS 15
-		59	#define LAGACY_INTERRUPT_BASE 0x20
57		60
58	/** General Exception codes. */	61	/** General Exception codes. */
59	#define GE_ILLEGALOP 0	62	#define GE_ILLEGALOP 0
60	#define GE_PRIVOP 1	63	#define GE_PRIVOP 1
61	#define GE_PRIVREG 2	64	#define GE_PRIVREG 2
62	#define GE_RESREGFLD 3	65	#define GE_RESREGFLD 3
63	#define GE_DISBLDISTRAN 4	66	#define GE_DISBLDISTRAN 4
64	#define GE_ILLEGALDEP 8	67	#define GE_ILLEGALDEP 8
65		68
66	#define EOI 0 /*< The actual value doesn't matter. /	69	#define EOI 0 /*< The actual value doesn't matter. /
67		70
68	typedef struct {	71	typedef struct {
69	uint128_t f2;	72	uint128_t f2;
70	uint128_t f3;	73	uint128_t f3;
71	uint128_t f4;	74	uint128_t f4;
72	uint128_t f5;	75	uint128_t f5;
73	uint128_t f6;	76	uint128_t f6;
74	uint128_t f7;	77	uint128_t f7;
75	uint128_t f8;	78	uint128_t f8;
76	uint128_t f9;	79	uint128_t f9;
77	uint128_t f10;	80	uint128_t f10;
78	uint128_t f11;	81	uint128_t f11;
79	uint128_t f12;	82	uint128_t f12;
80	uint128_t f13;	83	uint128_t f13;
81	uint128_t f14;	84	uint128_t f14;
82	uint128_t f15;	85	uint128_t f15;
83	uint128_t f16;	86	uint128_t f16;
84	uint128_t f17;	87	uint128_t f17;
85	uint128_t f18;	88	uint128_t f18;
86	uint128_t f19;	89	uint128_t f19;
87	uint128_t f20;	90	uint128_t f20;
88	uint128_t f21;	91	uint128_t f21;
89	uint128_t f22;	92	uint128_t f22;
90	uint128_t f23;	93	uint128_t f23;
91	uint128_t f24;	94	uint128_t f24;
92	uint128_t f25;	95	uint128_t f25;
93	uint128_t f26;	96	uint128_t f26;
94	uint128_t f27;	97	uint128_t f27;
95	uint128_t f28;	98	uint128_t f28;
96	uint128_t f29;	99	uint128_t f29;
97	uint128_t f30;	100	uint128_t f30;
98	uint128_t f31;	101	uint128_t f31;
99		102
100	uintptr_t ar_bsp;	103	uintptr_t ar_bsp;
101	uintptr_t ar_bspstore;	104	uintptr_t ar_bspstore;
102	uintptr_t ar_bspstore_new;	105	uintptr_t ar_bspstore_new;
103	uint64_t ar_rnat;	106	uint64_t ar_rnat;
104	uint64_t ar_ifs;	107	uint64_t ar_ifs;
105	uint64_t ar_pfs;	108	uint64_t ar_pfs;
106	uint64_t ar_rsc;	109	uint64_t ar_rsc;
107	uintptr_t cr_ifa;	110	uintptr_t cr_ifa;
108	cr_isr_t cr_isr;	111	cr_isr_t cr_isr;
109	uintptr_t cr_iipa;	112	uintptr_t cr_iipa;
110	psr_t cr_ipsr;	113	psr_t cr_ipsr;
111	uintptr_t cr_iip;	114	uintptr_t cr_iip;
112	uint64_t pr;	115	uint64_t pr;
113	uintptr_t sp;	116	uintptr_t sp;
114		117
115	/*	118	/*
116	* The following variables are defined only for break_instruction	119	* The following variables are defined only for break_instruction
117	* handler.	120	* handler.
118	*/	121	*/
119	uint64_t in0;	122	uint64_t in0;
120	uint64_t in1;	123	uint64_t in1;
121	uint64_t in2;	124	uint64_t in2;
122	uint64_t in3;	125	uint64_t in3;
123	uint64_t in4;	126	uint64_t in4;
124	uint64_t in5;	127	uint64_t in5;
125	uint64_t in6;	128	uint64_t in6;
126	} istate_t;	129	} istate_t;
127		130
128	static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)	131	static inline void istate_set_retaddr(istate_t *istate, uintptr_t retaddr)
129	{	132	{
130	istate->cr_iip = retaddr;	133	istate->cr_iip = retaddr;
131	istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */	134	istate->cr_ipsr.ri = 0; /* return to instruction slot #0 */
132	}	135	}
133		136
134	static inline unative_t istate_get_pc(istate_t *istate)	137	static inline unative_t istate_get_pc(istate_t *istate)
135	{	138	{
136	return istate->cr_iip;	139	return istate->cr_iip;
137	}	140	}
138		141
139	static inline int istate_from_uspace(istate_t *istate)	142	static inline int istate_from_uspace(istate_t *istate)
140	{	143	{
141	return (istate->cr_iip) < 0xe000000000000000ULL;	144	return (istate->cr_iip) < 0xe000000000000000ULL;
142	}	145	}
143		146
144	extern void *ivt;	147	extern void *ivt;
145		148
146	extern void general_exception(uint64_t vector, istate_t *istate);	149	extern void general_exception(uint64_t vector, istate_t *istate);
147	extern int break_instruction(uint64_t vector, istate_t *istate);	150	extern int break_instruction(uint64_t vector, istate_t *istate);
148	extern void universal_handler(uint64_t vector, istate_t *istate);	151	extern void universal_handler(uint64_t vector, istate_t *istate);
149	extern void nop_handler(uint64_t vector, istate_t *istate);	152	extern void nop_handler(uint64_t vector, istate_t *istate);
150	extern void external_interrupt(uint64_t vector, istate_t *istate);	153	extern void external_interrupt(uint64_t vector, istate_t *istate);
151	extern void disabled_fp_register(uint64_t vector, istate_t *istate);	154	extern void disabled_fp_register(uint64_t vector, istate_t *istate);
152		155
-		156
153	#endif	157	#endif
154		158
155	/** @}	159	/** @}
156	*/	160	*/
157		161

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(root)/branches/dynload/kernel/arch/ia64/include/interrupt.h – Rev 2927 → 3674