WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/ia64/include/asm.h


/*
 * Copyright (c) 2005 Jakub Jermar
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup ia64   
 * @{
 */
/** @file
 */
 
#ifndef KERN_ia64_ASM_H_
#define KERN_ia64_ASM_H_
 
#include <config.h>
#include <arch/types.h>
#include <arch/register.h>
 
#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
 
static inline void pio_write_8(ioport8_t *port, uint8_t v)
{
    uintptr_t prt = (uintptr_t) port;
 
    *((uint8_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline void pio_write_16(ioport16_t *port, uint16_t v)
{
    uintptr_t prt = (uintptr_t) port;
 
    *((uint16_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline void pio_write_32(ioport32_t *port, uint32_t v)
{
    uintptr_t prt = (uintptr_t) port;
 
    *((uint32_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12)))) = v;
 
    asm volatile ("mf\n" ::: "memory");
}
 
static inline uint8_t pio_read_8(ioport8_t *port)
{
    uintptr_t prt = (uintptr_t) port;
 
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint8_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12))));
}
 
static inline uint16_t pio_read_16(ioport16_t *port)
{
    uintptr_t prt = (uintptr_t) port;
 
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint16_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xffE) | ((prt >> 2) << 12))));
}
 
static inline uint32_t pio_read_32(ioport32_t *port)
{
    uintptr_t prt = (uintptr_t) port;
 
    asm volatile ("mf\n" ::: "memory");
 
    return *((uint32_t *)(IA64_IOSPACE_ADDRESS +
        ((prt & 0xfff) | ((prt >> 2) << 12))));
}
 
/** Return base address of current stack
 *
 * Return the base address of the current stack.
 * The stack is assumed to be STACK_SIZE long.
 * The stack must start on page boundary.
 */
static inline uintptr_t get_stack_base(void)
{
    uint64_t v;
 
    //I'm not sure why but this code bad inlines in scheduler, 
    //so THE shifts about 16B and causes kernel panic
    //asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
    //return v;
   
    //this code have the same meaning but inlines well
    asm volatile ("mov %0 = r12" : "=r" (v)  );
    return v & (~(STACK_SIZE-1));
}
 
/** Return Processor State Register.
 *
 * @return PSR.
 */
static inline uint64_t psr_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = psr\n" : "=r" (v));
   
    return v;
}
 
/** Read IVA (Interruption Vector Address).
 *
 * @return Return location of interruption vector table.
 */
static inline uint64_t iva_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
   
    return v;
}
 
/** Write IVA (Interruption Vector Address) register.
 *
 * @param v New location of interruption vector table.
 */
static inline void iva_write(uint64_t v)
{
    asm volatile ("mov cr.iva = %0\n" : : "r" (v));
}
 
 
/** Read IVR (External Interrupt Vector Register).
 *
 * @return Highest priority, pending, unmasked external interrupt vector.
 */
static inline uint64_t ivr_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
   
    return v;
}
 
static inline uint64_t cr64_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr64\n" : "=r" (v));
   
    return v;
}
 
 
/** Write ITC (Interval Timer Counter) register.
 *
 * @param v New counter value.
 */
static inline void itc_write(uint64_t v)
{
    asm volatile ("mov ar.itc = %0\n" : : "r" (v));
}
 
/** Read ITC (Interval Timer Counter) register.
 *
 * @return Current counter value.
 */
static inline uint64_t itc_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
   
    return v;
}
 
/** Write ITM (Interval Timer Match) register.
 *
 * @param v New match value.
 */
static inline void itm_write(uint64_t v)
{
    asm volatile ("mov cr.itm = %0\n" : : "r" (v));
}
 
/** Read ITM (Interval Timer Match) register.
 *
 * @return Match value.
 */
static inline uint64_t itm_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
   
    return v;
}
 
/** Read ITV (Interval Timer Vector) register.
 *
 * @return Current vector and mask bit.
 */
static inline uint64_t itv_read(void)
{
    uint64_t v;
   
    asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
   
    return v;
}
 
/** Write ITV (Interval Timer Vector) register.
 *
 * @param v New vector and mask bit.
 */
static inline void itv_write(uint64_t v)
{
    asm volatile ("mov cr.itv = %0\n" : : "r" (v));
}
 
/** Write EOI (End Of Interrupt) register.
 *
 * @param v This value is ignored.
 */
static inline void eoi_write(uint64_t v)
{
    asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
}
 
/** Read TPR (Task Priority Register).
 *
 * @return Current value of TPR.
 */
static inline uint64_t tpr_read(void)
{
    uint64_t v;
 
    asm volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
   
    return v;
}
 
/** Write TPR (Task Priority Register).
 *
 * @param v New value of TPR.
 */
static inline void tpr_write(uint64_t v)
{
    asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
}
 
/** Disable interrupts.
 *
 * Disable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 */
static ipl_t interrupts_disable(void)
{
    uint64_t v;
   
    asm volatile (
        "mov %0 = psr\n"
        "rsm %1\n"
        : "=r" (v)
        : "i" (PSR_I_MASK)
    );
   
    return (ipl_t) v;
}
 
/** Enable interrupts.
 *
 * Enable interrupts and return previous
 * value of PSR.
 *
 * @return Old interrupt priority level.
 */
static ipl_t interrupts_enable(void)
{
    uint64_t v;
   
    asm volatile (
        "mov %0 = psr\n"
        "ssm %1\n"
        ";;\n"
        "srlz.d\n"
        : "=r" (v)
        : "i" (PSR_I_MASK)
    );
   
    return (ipl_t) v;
}
 
/** Restore interrupt priority level.
 *
 * Restore PSR.
 *
 * @param ipl Saved interrupt priority level.
 */
static inline void interrupts_restore(ipl_t ipl)
{
    if (ipl & PSR_I_MASK)
        (void) interrupts_enable();
    else
        (void) interrupts_disable();
}
 
/** Return interrupt priority level.
 *
 * @return PSR.
 */
static inline ipl_t interrupts_read(void)
{
    return (ipl_t) psr_read();
}
 
/** Disable protection key checking. */
static inline void pk_disable(void)
{
    asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
}
 
extern void cpu_halt(void);
extern void cpu_sleep(void);
extern void asm_delay_loop(uint32_t t);
 
extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
    uint64_t, uint64_t);
 
#endif
 
/** @}
 */
 

Rev 4343	Rev 4344
1	/*	1	/*
2	* Copyright (c) 2005 Jakub Jermar	2	* Copyright (c) 2005 Jakub Jermar
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup ia64	29	/** @addtogroup ia64
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	*/	33	*/
34		34
35	#ifndef KERN_ia64_ASM_H_	35	#ifndef KERN_ia64_ASM_H_
36	#define KERN_ia64_ASM_H_	36	#define KERN_ia64_ASM_H_
37		37
38	#include <config.h>	38	#include <config.h>
39	#include <arch/types.h>	39	#include <arch/types.h>
40	#include <arch/register.h>	40	#include <arch/register.h>
41		41
42	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL	42	#define IA64_IOSPACE_ADDRESS 0xE001000000000000ULL
43		43
44	static inline void pio_write_8(ioport_t port, uint8_t v)	44	static inline void pio_write_8(ioport8_t *port, uint8_t v)
45	{	45	{
-		46	uintptr_t prt = (uintptr_t) port;
-		47
46	((uint8_t )(IA64_IOSPACE_ADDRESS +	48	((uint8_t )(IA64_IOSPACE_ADDRESS +
47	((port & 0xfff) \| ((port >> 2) << 12)))) = v;	49	((prt & 0xfff) \| ((prt >> 2) << 12)))) = v;
48		50
49	asm volatile ("mf\n" ::: "memory");	51	asm volatile ("mf\n" ::: "memory");
50	}	52	}
51		53
52	static inline void pio_write_16(ioport_t port, uint16_t v)	54	static inline void pio_write_16(ioport16_t *port, uint16_t v)
53	{	55	{
-		56	uintptr_t prt = (uintptr_t) port;
-		57
54	((uint16_t )(IA64_IOSPACE_ADDRESS +	58	((uint16_t )(IA64_IOSPACE_ADDRESS +
55	((port & 0xfff) \| ((port >> 2) << 12)))) = v;	59	((prt & 0xfff) \| ((prt >> 2) << 12)))) = v;
56		60
57	asm volatile ("mf\n" ::: "memory");	61	asm volatile ("mf\n" ::: "memory");
58	}	62	}
59		63
60	static inline void pio_write_32(ioport_t port, uint32_t v)	64	static inline void pio_write_32(ioport32_t *port, uint32_t v)
61	{	65	{
-		66	uintptr_t prt = (uintptr_t) port;
-		67
62	((uint32_t )(IA64_IOSPACE_ADDRESS +	68	((uint32_t )(IA64_IOSPACE_ADDRESS +
63	((port & 0xfff) \| ((port >> 2) << 12)))) = v;	69	((prt & 0xfff) \| ((prt >> 2) << 12)))) = v;
64		70
65	asm volatile ("mf\n" ::: "memory");	71	asm volatile ("mf\n" ::: "memory");
66	}	72	}
67		73
68	static inline uint8_t pio_read_8(ioport_t port)	74	static inline uint8_t pio_read_8(ioport8_t *port)
69	{	75	{
-		76	uintptr_t prt = (uintptr_t) port;
-		77
70	asm volatile ("mf\n" ::: "memory");	78	asm volatile ("mf\n" ::: "memory");
71		79
72	return ((uint8_t )(IA64_IOSPACE_ADDRESS +	80	return ((uint8_t )(IA64_IOSPACE_ADDRESS +
73	((port & 0xfff) \| ((port >> 2) << 12))));	81	((prt & 0xfff) \| ((prt >> 2) << 12))));
74	}	82	}
75		83
76	static inline uint16_t pio_read_16(ioport_t port)	84	static inline uint16_t pio_read_16(ioport16_t *port)
77	{	85	{
-		86	uintptr_t prt = (uintptr_t) port;
-		87
78	asm volatile ("mf\n" ::: "memory");	88	asm volatile ("mf\n" ::: "memory");
79		89
80	return ((uint16_t )(IA64_IOSPACE_ADDRESS +	90	return ((uint16_t )(IA64_IOSPACE_ADDRESS +
81	((port & 0xffE) \| ((port >> 2) << 12))));	91	((prt & 0xffE) \| ((prt >> 2) << 12))));
82	}	92	}
83		93
84	static inline uint32_t pio_read_32(ioport_t port)	94	static inline uint32_t pio_read_32(ioport32_t *port)
85	{	95	{
-		96	uintptr_t prt = (uintptr_t) port;
-		97
86	asm volatile ("mf\n" ::: "memory");	98	asm volatile ("mf\n" ::: "memory");
87		99
88	return ((uint32_t )(IA64_IOSPACE_ADDRESS +	100	return ((uint32_t )(IA64_IOSPACE_ADDRESS +
89	((port & 0xfff) \| ((port >> 2) << 12))));	101	((prt & 0xfff) \| ((prt >> 2) << 12))));
90	}	102	}
91		103
92	/** Return base address of current stack	104	/** Return base address of current stack
93	*	105	*
94	* Return the base address of the current stack.	106	* Return the base address of the current stack.
95	* The stack is assumed to be STACK_SIZE long.	107	* The stack is assumed to be STACK_SIZE long.
96	* The stack must start on page boundary.	108	* The stack must start on page boundary.
97	*/	109	*/
98	static inline uintptr_t get_stack_base(void)	110	static inline uintptr_t get_stack_base(void)
99	{	111	{
100	uint64_t v;	112	uint64_t v;
101		113
102	//I'm not sure why but this code bad inlines in scheduler,	114	//I'm not sure why but this code bad inlines in scheduler,
103	//so THE shifts about 16B and causes kernel panic	115	//so THE shifts about 16B and causes kernel panic
104	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));	116	//asm volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
105	//return v;	117	//return v;
106		118
107	//this code have the same meaning but inlines well	119	//this code have the same meaning but inlines well
108	asm volatile ("mov %0 = r12" : "=r" (v) );	120	asm volatile ("mov %0 = r12" : "=r" (v) );
109	return v & (~(STACK_SIZE-1));	121	return v & (~(STACK_SIZE-1));
110	}	122	}
111		123
112	/** Return Processor State Register.	124	/** Return Processor State Register.
113	*	125	*
114	* @return PSR.	126	* @return PSR.
115	*/	127	*/
116	static inline uint64_t psr_read(void)	128	static inline uint64_t psr_read(void)
117	{	129	{
118	uint64_t v;	130	uint64_t v;
119		131
120	asm volatile ("mov %0 = psr\n" : "=r" (v));	132	asm volatile ("mov %0 = psr\n" : "=r" (v));
121		133
122	return v;	134	return v;
123	}	135	}
124		136
125	/** Read IVA (Interruption Vector Address).	137	/** Read IVA (Interruption Vector Address).
126	*	138	*
127	* @return Return location of interruption vector table.	139	* @return Return location of interruption vector table.
128	*/	140	*/
129	static inline uint64_t iva_read(void)	141	static inline uint64_t iva_read(void)
130	{	142	{
131	uint64_t v;	143	uint64_t v;
132		144
133	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));	145	asm volatile ("mov %0 = cr.iva\n" : "=r" (v));
134		146
135	return v;	147	return v;
136	}	148	}
137		149
138	/** Write IVA (Interruption Vector Address) register.	150	/** Write IVA (Interruption Vector Address) register.
139	*	151	*
140	* @param v New location of interruption vector table.	152	* @param v New location of interruption vector table.
141	*/	153	*/
142	static inline void iva_write(uint64_t v)	154	static inline void iva_write(uint64_t v)
143	{	155	{
144	asm volatile ("mov cr.iva = %0\n" : : "r" (v));	156	asm volatile ("mov cr.iva = %0\n" : : "r" (v));
145	}	157	}
146		158
147		159
148	/** Read IVR (External Interrupt Vector Register).	160	/** Read IVR (External Interrupt Vector Register).
149	*	161	*
150	* @return Highest priority, pending, unmasked external interrupt vector.	162	* @return Highest priority, pending, unmasked external interrupt vector.
151	*/	163	*/
152	static inline uint64_t ivr_read(void)	164	static inline uint64_t ivr_read(void)
153	{	165	{
154	uint64_t v;	166	uint64_t v;
155		167
156	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));	168	asm volatile ("mov %0 = cr.ivr\n" : "=r" (v));
157		169
158	return v;	170	return v;
159	}	171	}
160		172
161	static inline uint64_t cr64_read(void)	173	static inline uint64_t cr64_read(void)
162	{	174	{
163	uint64_t v;	175	uint64_t v;
164		176
165	asm volatile ("mov %0 = cr64\n" : "=r" (v));	177	asm volatile ("mov %0 = cr64\n" : "=r" (v));
166		178
167	return v;	179	return v;
168	}	180	}
169		181
170		182
171	/** Write ITC (Interval Timer Counter) register.	183	/** Write ITC (Interval Timer Counter) register.
172	*	184	*
173	* @param v New counter value.	185	* @param v New counter value.
174	*/	186	*/
175	static inline void itc_write(uint64_t v)	187	static inline void itc_write(uint64_t v)
176	{	188	{
177	asm volatile ("mov ar.itc = %0\n" : : "r" (v));	189	asm volatile ("mov ar.itc = %0\n" : : "r" (v));
178	}	190	}
179		191
180	/** Read ITC (Interval Timer Counter) register.	192	/** Read ITC (Interval Timer Counter) register.
181	*	193	*
182	* @return Current counter value.	194	* @return Current counter value.
183	*/	195	*/
184	static inline uint64_t itc_read(void)	196	static inline uint64_t itc_read(void)
185	{	197	{
186	uint64_t v;	198	uint64_t v;
187		199
188	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));	200	asm volatile ("mov %0 = ar.itc\n" : "=r" (v));
189		201
190	return v;	202	return v;
191	}	203	}
192		204
193	/** Write ITM (Interval Timer Match) register.	205	/** Write ITM (Interval Timer Match) register.
194	*	206	*
195	* @param v New match value.	207	* @param v New match value.
196	*/	208	*/
197	static inline void itm_write(uint64_t v)	209	static inline void itm_write(uint64_t v)
198	{	210	{
199	asm volatile ("mov cr.itm = %0\n" : : "r" (v));	211	asm volatile ("mov cr.itm = %0\n" : : "r" (v));
200	}	212	}
201		213
202	/** Read ITM (Interval Timer Match) register.	214	/** Read ITM (Interval Timer Match) register.
203	*	215	*
204	* @return Match value.	216	* @return Match value.
205	*/	217	*/
206	static inline uint64_t itm_read(void)	218	static inline uint64_t itm_read(void)
207	{	219	{
208	uint64_t v;	220	uint64_t v;
209		221
210	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));	222	asm volatile ("mov %0 = cr.itm\n" : "=r" (v));
211		223
212	return v;	224	return v;
213	}	225	}
214		226
215	/** Read ITV (Interval Timer Vector) register.	227	/** Read ITV (Interval Timer Vector) register.
216	*	228	*
217	* @return Current vector and mask bit.	229	* @return Current vector and mask bit.
218	*/	230	*/
219	static inline uint64_t itv_read(void)	231	static inline uint64_t itv_read(void)
220	{	232	{
221	uint64_t v;	233	uint64_t v;
222		234
223	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));	235	asm volatile ("mov %0 = cr.itv\n" : "=r" (v));
224		236
225	return v;	237	return v;
226	}	238	}
227		239
228	/** Write ITV (Interval Timer Vector) register.	240	/** Write ITV (Interval Timer Vector) register.
229	*	241	*
230	* @param v New vector and mask bit.	242	* @param v New vector and mask bit.
231	*/	243	*/
232	static inline void itv_write(uint64_t v)	244	static inline void itv_write(uint64_t v)
233	{	245	{
234	asm volatile ("mov cr.itv = %0\n" : : "r" (v));	246	asm volatile ("mov cr.itv = %0\n" : : "r" (v));
235	}	247	}
236		248
237	/** Write EOI (End Of Interrupt) register.	249	/** Write EOI (End Of Interrupt) register.
238	*	250	*
239	* @param v This value is ignored.	251	* @param v This value is ignored.
240	*/	252	*/
241	static inline void eoi_write(uint64_t v)	253	static inline void eoi_write(uint64_t v)
242	{	254	{
243	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));	255	asm volatile ("mov cr.eoi = %0\n" : : "r" (v));
244	}	256	}
245		257
246	/** Read TPR (Task Priority Register).	258	/** Read TPR (Task Priority Register).
247	*	259	*
248	* @return Current value of TPR.	260	* @return Current value of TPR.
249	*/	261	*/
250	static inline uint64_t tpr_read(void)	262	static inline uint64_t tpr_read(void)
251	{	263	{
252	uint64_t v;	264	uint64_t v;
253		265
254	asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));	266	asm volatile ("mov %0 = cr.tpr\n" : "=r" (v));
255		267
256	return v;	268	return v;
257	}	269	}
258		270
259	/** Write TPR (Task Priority Register).	271	/** Write TPR (Task Priority Register).
260	*	272	*
261	* @param v New value of TPR.	273	* @param v New value of TPR.
262	*/	274	*/
263	static inline void tpr_write(uint64_t v)	275	static inline void tpr_write(uint64_t v)
264	{	276	{
265	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));	277	asm volatile ("mov cr.tpr = %0\n" : : "r" (v));
266	}	278	}
267		279
268	/** Disable interrupts.	280	/** Disable interrupts.
269	*	281	*
270	* Disable interrupts and return previous	282	* Disable interrupts and return previous
271	* value of PSR.	283	* value of PSR.
272	*	284	*
273	* @return Old interrupt priority level.	285	* @return Old interrupt priority level.
274	*/	286	*/
275	static ipl_t interrupts_disable(void)	287	static ipl_t interrupts_disable(void)
276	{	288	{
277	uint64_t v;	289	uint64_t v;
278		290
279	asm volatile (	291	asm volatile (
280	"mov %0 = psr\n"	292	"mov %0 = psr\n"
281	"rsm %1\n"	293	"rsm %1\n"
282	: "=r" (v)	294	: "=r" (v)
283	: "i" (PSR_I_MASK)	295	: "i" (PSR_I_MASK)
284	);	296	);
285		297
286	return (ipl_t) v;	298	return (ipl_t) v;
287	}	299	}
288		300
289	/** Enable interrupts.	301	/** Enable interrupts.
290	*	302	*
291	* Enable interrupts and return previous	303	* Enable interrupts and return previous
292	* value of PSR.	304	* value of PSR.
293	*	305	*
294	* @return Old interrupt priority level.	306	* @return Old interrupt priority level.
295	*/	307	*/
296	static ipl_t interrupts_enable(void)	308	static ipl_t interrupts_enable(void)
297	{	309	{
298	uint64_t v;	310	uint64_t v;
299		311
300	asm volatile (	312	asm volatile (
301	"mov %0 = psr\n"	313	"mov %0 = psr\n"
302	"ssm %1\n"	314	"ssm %1\n"
303	";;\n"	315	";;\n"
304	"srlz.d\n"	316	"srlz.d\n"
305	: "=r" (v)	317	: "=r" (v)
306	: "i" (PSR_I_MASK)	318	: "i" (PSR_I_MASK)
307	);	319	);
308		320
309	return (ipl_t) v;	321	return (ipl_t) v;
310	}	322	}
311		323
312	/** Restore interrupt priority level.	324	/** Restore interrupt priority level.
313	*	325	*
314	* Restore PSR.	326	* Restore PSR.
315	*	327	*
316	* @param ipl Saved interrupt priority level.	328	* @param ipl Saved interrupt priority level.
317	*/	329	*/
318	static inline void interrupts_restore(ipl_t ipl)	330	static inline void interrupts_restore(ipl_t ipl)
319	{	331	{
320	if (ipl & PSR_I_MASK)	332	if (ipl & PSR_I_MASK)
321	(void) interrupts_enable();	333	(void) interrupts_enable();
322	else	334	else
323	(void) interrupts_disable();	335	(void) interrupts_disable();
324	}	336	}
325		337
326	/** Return interrupt priority level.	338	/** Return interrupt priority level.
327	*	339	*
328	* @return PSR.	340	* @return PSR.
329	*/	341	*/
330	static inline ipl_t interrupts_read(void)	342	static inline ipl_t interrupts_read(void)
331	{	343	{
332	return (ipl_t) psr_read();	344	return (ipl_t) psr_read();
333	}	345	}
334		346
335	/** Disable protection key checking. */	347	/** Disable protection key checking. */
336	static inline void pk_disable(void)	348	static inline void pk_disable(void)
337	{	349	{
338	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));	350	asm volatile ("rsm %0\n" : : "i" (PSR_PK_MASK));
339	}	351	}
340		352
341	extern void cpu_halt(void);	353	extern void cpu_halt(void);
342	extern void cpu_sleep(void);	354	extern void cpu_sleep(void);
343	extern void asm_delay_loop(uint32_t t);	355	extern void asm_delay_loop(uint32_t t);
344		356
345	extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,	357	extern void switch_to_userspace(uintptr_t, uintptr_t, uintptr_t, uintptr_t,
346	uint64_t, uint64_t);	358	uint64_t, uint64_t);
347		359
348	#endif	360	#endif
349		361
350	/** @}	362	/** @}
351	*/	363	*/
352		364

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(root)/branches/dynload/kernel/arch/ia64/include/asm.h – Rev 4343 → 4344