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| 1 | /* |
1 | /* |
| 2 | * Copyright (c) 2007 Petr Stepan |
2 | * Copyright (c) 2007 Petr Stepan |
| 3 | * All rights reserved. |
3 | * All rights reserved. |
| 4 | * |
4 | * |
| 5 | * Redistribution and use in source and binary forms, with or without |
5 | * Redistribution and use in source and binary forms, with or without |
| 6 | * modification, are permitted provided that the following conditions |
6 | * modification, are permitted provided that the following conditions |
| 7 | * are met: |
7 | * are met: |
| 8 | * |
8 | * |
| 9 | * - Redistributions of source code must retain the above copyright |
9 | * - Redistributions of source code must retain the above copyright |
| 10 | * notice, this list of conditions and the following disclaimer. |
10 | * notice, this list of conditions and the following disclaimer. |
| 11 | * - Redistributions in binary form must reproduce the above copyright |
11 | * - Redistributions in binary form must reproduce the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer in the |
12 | * notice, this list of conditions and the following disclaimer in the |
| 13 | * documentation and/or other materials provided with the distribution. |
13 | * documentation and/or other materials provided with the distribution. |
| 14 | * - The name of the author may not be used to endorse or promote products |
14 | * - The name of the author may not be used to endorse or promote products |
| 15 | * derived from this software without specific prior written permission. |
15 | * derived from this software without specific prior written permission. |
| 16 | * |
16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
17 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR |
| 18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
18 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES |
| 19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
19 | * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
| 20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
20 | * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
| 21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
21 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
| 22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
22 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
23 | * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
24 | * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | */ |
27 | */ |
| 28 | 28 | ||
| 29 | /** @addtogroup arm32 |
29 | /** @addtogroup arm32 |
| 30 | * @{ |
30 | * @{ |
| 31 | */ |
31 | */ |
| 32 | /** @file |
32 | /** @file |
| 33 | * @brief Interrupts controlling routines. |
33 | * @brief Interrupts controlling routines. |
| 34 | */ |
34 | */ |
| 35 | 35 | ||
| 36 | #include <arch/asm.h> |
36 | #include <arch/asm.h> |
| 37 | #include <arch/regutils.h> |
37 | #include <arch/regutils.h> |
| - | 38 | #include <arch/drivers/gxemul.h> |
|
| 38 | #include <ddi/irq.h> |
39 | #include <ddi/irq.h> |
| 39 | #include <arch/machine.h> |
40 | #include <ddi/device.h> |
| 40 | #include <interrupt.h> |
41 | #include <interrupt.h> |
| 41 | 42 | ||
| 42 | /** Initial size of a table holding interrupt handlers. */ |
43 | /** Initial size of a table holding interrupt handlers. */ |
| 43 | #define IRQ_COUNT 8 |
44 | #define IRQ_COUNT 8 |
| 44 | 45 | ||
| - | 46 | static irq_t gxemul_timer_irq; |
|
| - | 47 | ||
| 45 | /** Disable interrupts. |
48 | /** Disable interrupts. |
| 46 | * |
49 | * |
| 47 | * @return Old interrupt priority level. |
50 | * @return Old interrupt priority level. |
| 48 | */ |
51 | */ |
| 49 | ipl_t interrupts_disable(void) |
52 | ipl_t interrupts_disable(void) |
| 50 | { |
53 | { |
| 51 | ipl_t ipl = current_status_reg_read(); |
54 | ipl_t ipl = current_status_reg_read(); |
| 52 | 55 | ||
| 53 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
56 | current_status_reg_control_write(STATUS_REG_IRQ_DISABLED_BIT | ipl); |
| 54 | 57 | ||
| 55 | return ipl; |
58 | return ipl; |
| 56 | } |
59 | } |
| 57 | 60 | ||
| 58 | /** Enable interrupts. |
61 | /** Enable interrupts. |
| 59 | * |
62 | * |
| 60 | * @return Old interrupt priority level. |
63 | * @return Old interrupt priority level. |
| 61 | */ |
64 | */ |
| 62 | ipl_t interrupts_enable(void) |
65 | ipl_t interrupts_enable(void) |
| 63 | { |
66 | { |
| 64 | ipl_t ipl = current_status_reg_read(); |
67 | ipl_t ipl = current_status_reg_read(); |
| 65 | 68 | ||
| 66 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
69 | current_status_reg_control_write(ipl & ~STATUS_REG_IRQ_DISABLED_BIT); |
| 67 | 70 | ||
| 68 | return ipl; |
71 | return ipl; |
| 69 | } |
72 | } |
| 70 | 73 | ||
| 71 | /** Restore interrupt priority level. |
74 | /** Restore interrupt priority level. |
| 72 | * |
75 | * |
| 73 | * @param ipl Saved interrupt priority level. |
76 | * @param ipl Saved interrupt priority level. |
| 74 | */ |
77 | */ |
| 75 | void interrupts_restore(ipl_t ipl) |
78 | void interrupts_restore(ipl_t ipl) |
| 76 | { |
79 | { |
| 77 | current_status_reg_control_write( |
80 | current_status_reg_control_write( |
| 78 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | |
81 | (current_status_reg_read() & ~STATUS_REG_IRQ_DISABLED_BIT) | |
| 79 | (ipl & STATUS_REG_IRQ_DISABLED_BIT)); |
82 | (ipl & STATUS_REG_IRQ_DISABLED_BIT)); |
| 80 | } |
83 | } |
| 81 | 84 | ||
| 82 | /** Read interrupt priority level. |
85 | /** Read interrupt priority level. |
| 83 | * |
86 | * |
| 84 | * @return Current interrupt priority level. |
87 | * @return Current interrupt priority level. |
| 85 | */ |
88 | */ |
| 86 | ipl_t interrupts_read(void) |
89 | ipl_t interrupts_read(void) |
| 87 | { |
90 | { |
| 88 | return current_status_reg_read(); |
91 | return current_status_reg_read(); |
| 89 | } |
92 | } |
| 90 | 93 | ||
| - | 94 | /** Starts gxemul Real Time Clock device, which asserts regular interrupts. |
|
| - | 95 | * |
|
| - | 96 | * @param frequency Interrupts frequency (0 disables RTC). |
|
| - | 97 | */ |
|
| - | 98 | static void gxemul_timer_start(uint32_t frequency) |
|
| - | 99 | { |
|
| - | 100 | *((uint32_t *) (gxemul_rtc + GXEMUL_RTC_FREQ_OFFSET)) |
|
| - | 101 | = frequency; |
|
| - | 102 | } |
|
| - | 103 | ||
| - | 104 | static irq_ownership_t gxemul_timer_claim(irq_t *irq) |
|
| - | 105 | { |
|
| - | 106 | return IRQ_ACCEPT; |
|
| - | 107 | } |
|
| - | 108 | ||
| - | 109 | /** Timer interrupt handler. |
|
| - | 110 | * |
|
| - | 111 | * @param irq Interrupt information. |
|
| - | 112 | * @param arg Not used. |
|
| - | 113 | */ |
|
| - | 114 | static void gxemul_timer_irq_handler(irq_t *irq) |
|
| - | 115 | { |
|
| - | 116 | /* |
|
| - | 117 | * We are holding a lock which prevents preemption. |
|
| - | 118 | * Release the lock, call clock() and reacquire the lock again. |
|
| - | 119 | */ |
|
| - | 120 | spinlock_unlock(&irq->lock); |
|
| - | 121 | clock(); |
|
| - | 122 | spinlock_lock(&irq->lock); |
|
| - | 123 | ||
| - | 124 | /* acknowledge tick */ |
|
| - | 125 | *((uint32_t *) (gxemul_rtc + GXEMUL_RTC_ACK_OFFSET)) |
|
| - | 126 | = 0; |
|
| - | 127 | } |
|
| - | 128 | ||
| 91 | /** Initialize basic tables for exception dispatching |
129 | /** Initialize basic tables for exception dispatching |
| 92 | * and starts the timer. |
130 | * and starts the timer. |
| 93 | */ |
131 | */ |
| 94 | void interrupt_init(void) |
132 | void interrupt_init(void) |
| 95 | { |
133 | { |
| 96 | irq_init(IRQ_COUNT, IRQ_COUNT); |
134 | irq_init(IRQ_COUNT, IRQ_COUNT); |
| - | 135 | ||
| - | 136 | irq_initialize(&gxemul_timer_irq); |
|
| - | 137 | gxemul_timer_irq.devno = device_assign_devno(); |
|
| - | 138 | gxemul_timer_irq.inr = GXEMUL_TIMER_IRQ; |
|
| - | 139 | gxemul_timer_irq.claim = gxemul_timer_claim; |
|
| - | 140 | gxemul_timer_irq.handler = gxemul_timer_irq_handler; |
|
| - | 141 | ||
| 97 | machine_timer_irq_start(); |
142 | irq_register(&gxemul_timer_irq); |
| - | 143 | ||
| - | 144 | gxemul_timer_start(GXEMUL_TIMER_FREQ); |
|
| 98 | } |
145 | } |
| 99 | 146 | ||
| 100 | /** @} |
147 | /** @} |
| 101 | */ |
148 | */ |
| 102 | 149 | ||