WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/arm32/src/exception.c


/*
 * Copyright (c) 2007 Petr Stepan
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup arm32
 * @{
 */
/** @file
 *  @brief Exception handlers and exception initialization routines.
 */
 
#include <arch/exception.h>
#include <arch/debug/print.h>
#include <arch/memstr.h>
#include <arch/regutils.h>
#include <interrupt.h>
#include <arch/machine.h>
#include <arch/mm/page_fault.h>
#include <arch/barrier.h>
#include <print.h>
#include <syscall/syscall.h>
 
/** Offset used in calculation of exception handler's relative address.
 *
 * @see install_handler()
 */
#define PREFETCH_OFFSET      0x8
 
/** LDR instruction's code */
#define LDR_OPCODE           0xe59ff000
 
/** Number of exception vectors. */
#define EXC_VECTORS          8
 
/** Size of memory block occupied by exception vectors. */
#define EXC_VECTORS_SIZE     (EXC_VECTORS * 4)
 
/** Switches to kernel stack and saves all registers there.
 *
 * Temporary exception stack is used to save a few registers
 * before stack switch takes place.
 *
 */
inline static void setup_stack_and_save_regs()
{
    asm volatile (
        "ldr r13, =exc_stack\n"
        "stmfd r13!, {r0}\n"
        "mrs r0, spsr\n"
        "and r0, r0, #0x1f\n"
        "cmp r0, #0x10\n"
        "bne 1f\n"
       
        /* prev mode was usermode */
        "ldmfd r13!, {r0}\n"
        "ldr r13, =supervisor_sp\n"
        "ldr r13, [r13]\n"
        "stmfd r13!, {lr}\n"
        "stmfd r13!, {r0-r12}\n"
        "stmfd r13!, {r13, lr}^\n"
        "mrs r0, spsr\n"
        "stmfd r13!, {r0}\n"
        "b 2f\n"
       
        /* mode was not usermode */
        "1:\n"
            "stmfd r13!, {r1, r2, r3}\n"
            "mrs r1, cpsr\n"
            "mov r2, lr\n"
            "bic r1, r1, #0x1f\n"
            "orr r1, r1, r0\n"
            "mrs r0, cpsr\n"
            "msr cpsr_c, r1\n"
           
            "mov r3, r13\n"
            "stmfd r13!, {r2}\n"
            "mov r2, lr\n"
            "stmfd r13!, {r4-r12}\n"
            "mov r1, r13\n"
           
            /* the following two lines are for debugging */
            "mov sp, #0\n"
            "mov lr, #0\n"
            "msr cpsr_c, r0\n"
           
            "ldmfd r13!, {r4, r5, r6, r7}\n"
            "stmfd r1!, {r4, r5, r6}\n"
            "stmfd r1!, {r7}\n"
            "stmfd r1!, {r2}\n"
            "stmfd r1!, {r3}\n"
            "mrs r0, spsr\n"
            "stmfd r1!, {r0}\n"
            "mov r13, r1\n"
           
        "2:\n"
    );
}
 
/** Returns from exception mode.
 *
 * Previously saved state of registers (including control register)
 * is restored from the stack.
 */
inline static void load_regs()
{
    asm volatile(
        "ldmfd r13!, {r0}       \n"
        "msr spsr, r0           \n"
        "and r0, r0, #0x1f      \n"
        "cmp r0, #0x10          \n"
        "bne 1f             \n"
 
        /* return to user mode */
        "ldmfd r13!, {r13, lr}^     \n"
        "b 2f               \n"
 
        /* return to non-user mode */
    "1:\n"
        "ldmfd r13!, {r1, r2}       \n"
        "mrs r3, cpsr           \n"
        "bic r3, r3, #0x1f      \n"
        "orr r3, r3, r0         \n"
        "mrs r0, cpsr           \n"
        "msr cpsr_c, r3         \n"
 
        "mov r13, r1            \n"
        "mov lr, r2         \n"
        "msr cpsr_c, r0         \n"
 
        /* actual return */
    "2:\n"
        "ldmfd r13, {r0-r12, pc}^\n"
    );
}
 
 
/** Switch CPU to mode in which interrupts are serviced (currently it
 * is Undefined mode).
 *
 * The default mode for interrupt servicing (Interrupt Mode)
 * can not be used because of nested interrupts (which can occur
 * because interrupts are enabled in higher levels of interrupt handler).
 */
inline static void switch_to_irq_servicing_mode()
{
    /* switch to Undefined mode */
    asm volatile(
        /* save regs used during switching */
        "stmfd sp!, {r0-r3}     \n"
 
        /* save stack pointer and link register to r1, r2 */
        "mov r1, sp         \n"
        "mov r2, lr         \n"
 
        /* mode switch */
        "mrs r0, cpsr           \n"
        "bic r0, r0, #0x1f      \n"
        "orr r0, r0, #0x1b      \n"
        "msr cpsr_c, r0         \n"
 
        /* restore saved sp and lr */
        "mov sp, r1         \n"
        "mov lr, r2         \n"
 
        /* restore original regs */
        "ldmfd sp!, {r0-r3}     \n"
    );
}
 
/** Calls exception dispatch routine. */
#define CALL_EXC_DISPATCH(exception) \
    asm volatile ( \
        "mov r0, %[exc]\n" \
        "mov r1, r13\n" \
        "bl exc_dispatch\n" \
        :: [exc] "i" (exception) \
    );\
 
/** General exception handler.
 *
 *  Stores registers, dispatches the exception,
 *  and finally restores registers and returns from exception processing.
 *
 *  @param exception Exception number.
 */
#define PROCESS_EXCEPTION(exception) \
    setup_stack_and_save_regs(); \
    CALL_EXC_DISPATCH(exception) \
    load_regs();
 
/** Updates specified exception vector to jump to given handler.
 *
 *  Addresses of handlers are stored in memory following exception vectors.
 */
static void install_handler(unsigned handler_addr, unsigned *vector)
{
    /* relative address (related to exc. vector) of the word
     * where handler's address is stored
    */
    volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
        PREFETCH_OFFSET;
   
    /* make it LDR instruction and store at exception vector */
    *vector = handler_address_ptr | LDR_OPCODE;
    smc_coherence(*vector);
   
    /* store handler's address */
    *(vector + EXC_VECTORS) = handler_addr;
 
}
 
/** Low-level Reset Exception handler. */
static void reset_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_RESET);
}
 
/** Low-level Software Interrupt Exception handler. */
static void swi_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_SWI);
}
 
/** Low-level Undefined Instruction Exception handler. */
static void undef_instr_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
}
 
/** Low-level Fast Interrupt Exception handler. */
static void fiq_exception_entry(void)
{
    PROCESS_EXCEPTION(EXC_FIQ);
}
 
/** Low-level Prefetch Abort Exception handler. */
static void prefetch_abort_exception_entry(void)
{
    asm("sub lr, lr, #4");
    PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
}
 
/** Low-level Data Abort Exception handler. */
static void data_abort_exception_entry(void)
{
    asm("sub lr, lr, #8");
    PROCESS_EXCEPTION(EXC_DATA_ABORT);
}
 
/** Low-level Interrupt Exception handler.
 *
 * CPU is switched to Undefined mode before further interrupt processing
 * because of possible occurence of nested interrupt exception, which
 * would overwrite (and thus spoil) stack pointer.
 */
static void irq_exception_entry(void)
{
    asm("sub lr, lr, #4");
    setup_stack_and_save_regs();
   
    switch_to_irq_servicing_mode();
   
    CALL_EXC_DISPATCH(EXC_IRQ)
 
    load_regs();
}
 
/** Software Interrupt handler.
 *
 * Dispatches the syscall.
 */
static void swi_exception(int exc_no, istate_t *istate)
{
    istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
        istate->r3, istate->r4, istate->r5, istate->r6);
}
 
/** Interrupt Exception handler.
 *
 * Determines the sources of interrupt and calls their handlers.
 */
static void irq_exception(int exc_no, istate_t *istate)
{
    machine_irq_exception(exc_no, istate);
}
 
/** Fills exception vectors with appropriate exception handlers. */
void install_exception_handlers(void)
{
    install_handler((unsigned) reset_exception_entry,
        (unsigned *) EXC_RESET_VEC);
   
    install_handler((unsigned) undef_instr_exception_entry,
        (unsigned *) EXC_UNDEF_INSTR_VEC);
   
    install_handler((unsigned) swi_exception_entry,
        (unsigned *) EXC_SWI_VEC);
   
    install_handler((unsigned) prefetch_abort_exception_entry,
        (unsigned *) EXC_PREFETCH_ABORT_VEC);
   
    install_handler((unsigned) data_abort_exception_entry,
        (unsigned *) EXC_DATA_ABORT_VEC);
   
    install_handler((unsigned) irq_exception_entry,
        (unsigned *) EXC_IRQ_VEC);
   
    install_handler((unsigned)fiq_exception_entry,
        (unsigned *) EXC_FIQ_VEC);
}
 
#ifdef HIGH_EXCEPTION_VECTORS
/** Activates use of high exception vectors addresses. */
static void high_vectors(void)
{
    uint32_t control_reg;
   
    asm volatile (
        "mrc p15, 0, %[control_reg], c1, c1"
        : [control_reg] "=r" (control_reg)
    );
   
    /* switch on the high vectors bit */
    control_reg |= CP15_R1_HIGH_VECTORS_BIT;
   
    asm volatile (
        "mcr p15, 0, %[control_reg], c1, c1"
        :: [control_reg] "r" (control_reg)
    );
}
#endif
 
/** Initializes exception handling.
 *
 * Installs low-level exception handlers and then registers
 * exceptions and their handlers to kernel exception dispatcher.
 */
void exception_init(void)
{
#ifdef HIGH_EXCEPTION_VECTORS
    high_vectors();
#endif
    install_exception_handlers();
   
    exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
    exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
        (iroutine) prefetch_abort);
    exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
    exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
}
 
/** Prints #istate_t structure content.
 *
 * @param istate Structure to be printed.
 */
void print_istate(istate_t *istate)
{
    dprintf("istate dump:\n");
 
    dprintf(" r0: %x    r1: %x    r2: %x    r3: %x\n",
        istate->r0, istate->r1, istate->r2, istate->r3);
    dprintf(" r4: %x    r5: %x    r6: %x    r7: %x\n",
        istate->r4, istate->r5, istate->r6, istate->r7);
    dprintf(" r8: %x    r8: %x   r10: %x   r11: %x\n",
        istate->r8, istate->r9, istate->r10, istate->r11);
    dprintf(" r12: %x    sp: %x    lr: %x  spsr: %x\n",
        istate->r12, istate->sp, istate->lr, istate->spsr);
 
    dprintf(" pc: %x\n", istate->pc);
}
 
/** @}
 */
 

Rev 3153	Rev 4345
1	/*	1	/*
2	* Copyright (c) 2007 Petr Stepan	2	* Copyright (c) 2007 Petr Stepan
3	* All rights reserved.	3	* All rights reserved.
4	*	4	*
5	* Redistribution and use in source and binary forms, with or without	5	* Redistribution and use in source and binary forms, with or without
6	* modification, are permitted provided that the following conditions	6	* modification, are permitted provided that the following conditions
7	* are met:	7	* are met:
8	*	8	*
9	* - Redistributions of source code must retain the above copyright	9	* - Redistributions of source code must retain the above copyright
10	* notice, this list of conditions and the following disclaimer.	10	* notice, this list of conditions and the following disclaimer.
11	* - Redistributions in binary form must reproduce the above copyright	11	* - Redistributions in binary form must reproduce the above copyright
12	* notice, this list of conditions and the following disclaimer in the	12	* notice, this list of conditions and the following disclaimer in the
13	* documentation and/or other materials provided with the distribution.	13	* documentation and/or other materials provided with the distribution.
14	* - The name of the author may not be used to endorse or promote products	14	* - The name of the author may not be used to endorse or promote products
15	* derived from this software without specific prior written permission.	15	* derived from this software without specific prior written permission.
16	*	16	*
17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	17	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	18	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	19	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	20	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	21	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	22	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	23	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	24	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	25	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	26	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27	*/	27	*/
28		28
29	/** @addtogroup arm32	29	/** @addtogroup arm32
30	* @{	30	* @{
31	*/	31	*/
32	/** @file	32	/** @file
33	* @brief Exception handlers and exception initialization routines.	33	* @brief Exception handlers and exception initialization routines.
34	*/	34	*/
35		35
36	#include <arch/exception.h>	36	#include <arch/exception.h>
37	#include <arch/debug/print.h>	37	#include <arch/debug/print.h>
38	#include <arch/memstr.h>	38	#include <arch/memstr.h>
39	#include <arch/regutils.h>	39	#include <arch/regutils.h>
40	#include <interrupt.h>	40	#include <interrupt.h>
41	#include <arch/machine.h>	41	#include <arch/machine.h>
42	#include <arch/mm/page_fault.h>	42	#include <arch/mm/page_fault.h>
43	#include <arch/barrier.h>	43	#include <arch/barrier.h>
44	#include <print.h>	44	#include <print.h>
45	#include <syscall/syscall.h>	45	#include <syscall/syscall.h>
46		46
47	/** Offset used in calculation of exception handler's relative address.	47	/** Offset used in calculation of exception handler's relative address.
48	*	48	*
49	* @see install_handler()	49	* @see install_handler()
50	*/	50	*/
51	#define PREFETCH_OFFSET 0x8	51	#define PREFETCH_OFFSET 0x8
52		52
53	/** LDR instruction's code */	53	/** LDR instruction's code */
54	#define LDR_OPCODE 0xe59ff000	54	#define LDR_OPCODE 0xe59ff000
55		55
56	/** Number of exception vectors. */	56	/** Number of exception vectors. */
57	#define EXC_VECTORS 8	57	#define EXC_VECTORS 8
58		58
59	/** Size of memory block occupied by exception vectors. */	59	/** Size of memory block occupied by exception vectors. */
60	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)	60	#define EXC_VECTORS_SIZE (EXC_VECTORS * 4)
61		61
62	/** Switches to kernel stack and saves all registers there.	62	/** Switches to kernel stack and saves all registers there.
63	*	63	*
64	* Temporary exception stack is used to save a few registers	64	* Temporary exception stack is used to save a few registers
65	* before stack switch takes place.	65	* before stack switch takes place.
-		66	*
66	*/	67	*/
67	inline static void setup_stack_and_save_regs()	68	inline static void setup_stack_and_save_regs()
68	{	69	{
69	asm volatile(	70	asm volatile (
70	"ldr r13, =exc_stack \n"	71	"ldr r13, =exc_stack\n"
71	"stmfd r13!, {r0} \n"	72	"stmfd r13!, {r0}\n"
72	"mrs r0, spsr \n"	73	"mrs r0, spsr\n"
73	"and r0, r0, #0x1f \n"	74	"and r0, r0, #0x1f\n"
74	"cmp r0, #0x10 \n"	75	"cmp r0, #0x10\n"
75	"bne 1f \n"	76	"bne 1f\n"
76		77
77	/* prev mode was usermode */	78	/* prev mode was usermode */
78	"ldmfd r13!, {r0} \n"	79	"ldmfd r13!, {r0}\n"
79	"ldr r13, =supervisor_sp \n"	80	"ldr r13, =supervisor_sp\n"
80	"ldr r13, [r13] \n"	81	"ldr r13, [r13]\n"
81	"stmfd r13!, {lr} \n"	82	"stmfd r13!, {lr}\n"
82	"stmfd r13!, {r0-r12} \n"	83	"stmfd r13!, {r0-r12}\n"
83	"stmfd r13!, {r13, lr}^ \n"	84	"stmfd r13!, {r13, lr}^\n"
84	"mrs r0, spsr \n"	85	"mrs r0, spsr\n"
85	"stmfd r13!, {r0} \n"	86	"stmfd r13!, {r0}\n"
86	"b 2f \n"	87	"b 2f\n"
87		88
88	/* mode was not usermode */	89	/* mode was not usermode */
89	"1:\n"	90	"1:\n"
90	"stmfd r13!, {r1, r2, r3} \n"	91	"stmfd r13!, {r1, r2, r3}\n"
91	"mrs r1, cpsr \n"	92	"mrs r1, cpsr\n"
92	"mov r2, lr \n"	93	"mov r2, lr\n"
93	"bic r1, r1, #0x1f \n"	94	"bic r1, r1, #0x1f\n"
94	"orr r1, r1, r0 \n"	95	"orr r1, r1, r0\n"
95	"mrs r0, cpsr \n"	96	"mrs r0, cpsr\n"
96	"msr cpsr_c, r1 \n"	97	"msr cpsr_c, r1\n"
97		98
98	"mov r3, r13 \n"	99	"mov r3, r13\n"
99	"stmfd r13!, {r2} \n"	100	"stmfd r13!, {r2}\n"
100	"mov r2, lr \n"	101	"mov r2, lr\n"
101	"stmfd r13!, {r4-r12} \n"	102	"stmfd r13!, {r4-r12}\n"
102	"mov r1, r13 \n"	103	"mov r1, r13\n"
-		104
103	/* the following two lines are for debugging */	105	/* the following two lines are for debugging */
104	"mov sp, #0 \n"	106	"mov sp, #0\n"
105	"mov lr, #0 \n"	107	"mov lr, #0\n"
106	"msr cpsr_c, r0 \n"	108	"msr cpsr_c, r0\n"
107		109
108	"ldmfd r13!, {r4, r5, r6, r7} \n"	110	"ldmfd r13!, {r4, r5, r6, r7}\n"
109	"stmfd r1!, {r4, r5, r6} \n"	111	"stmfd r1!, {r4, r5, r6}\n"
110	"stmfd r1!, {r7} \n"	112	"stmfd r1!, {r7}\n"
111	"stmfd r1!, {r2} \n"	113	"stmfd r1!, {r2}\n"
112	"stmfd r1!, {r3} \n"	114	"stmfd r1!, {r3}\n"
113	"mrs r0, spsr \n"	115	"mrs r0, spsr\n"
114	"stmfd r1!, {r0} \n"	116	"stmfd r1!, {r0}\n"
115	"mov r13, r1 \n"	117	"mov r13, r1\n"
-		118
116	"2:\n"	119	"2:\n"
117	);	120	);
118	}	121	}
119		122
120	/** Returns from exception mode.	123	/** Returns from exception mode.
121	*	124	*
122	* Previously saved state of registers (including control register)	125	* Previously saved state of registers (including control register)
123	* is restored from the stack.	126	* is restored from the stack.
124	*/	127	*/
125	inline static void load_regs()	128	inline static void load_regs()
126	{	129	{
127	asm volatile(	130	asm volatile(
128	"ldmfd r13!, {r0} \n"	131	"ldmfd r13!, {r0} \n"
129	"msr spsr, r0 \n"	132	"msr spsr, r0 \n"
130	"and r0, r0, #0x1f \n"	133	"and r0, r0, #0x1f \n"
131	"cmp r0, #0x10 \n"	134	"cmp r0, #0x10 \n"
132	"bne 1f \n"	135	"bne 1f \n"
133		136
134	/* return to user mode */	137	/* return to user mode */
135	"ldmfd r13!, {r13, lr}^ \n"	138	"ldmfd r13!, {r13, lr}^ \n"
136	"b 2f \n"	139	"b 2f \n"
137		140
138	/* return to non-user mode */	141	/* return to non-user mode */
139	"1:\n"	142	"1:\n"
140	"ldmfd r13!, {r1, r2} \n"	143	"ldmfd r13!, {r1, r2} \n"
141	"mrs r3, cpsr \n"	144	"mrs r3, cpsr \n"
142	"bic r3, r3, #0x1f \n"	145	"bic r3, r3, #0x1f \n"
143	"orr r3, r3, r0 \n"	146	"orr r3, r3, r0 \n"
144	"mrs r0, cpsr \n"	147	"mrs r0, cpsr \n"
145	"msr cpsr_c, r3 \n"	148	"msr cpsr_c, r3 \n"
146		149
147	"mov r13, r1 \n"	150	"mov r13, r1 \n"
148	"mov lr, r2 \n"	151	"mov lr, r2 \n"
149	"msr cpsr_c, r0 \n"	152	"msr cpsr_c, r0 \n"
150		153
151	/* actual return */	154	/* actual return */
152	"2:\n"	155	"2:\n"
153	"ldmfd r13, {r0-r12, pc}^\n"	156	"ldmfd r13, {r0-r12, pc}^\n"
154	);	157	);
155	}	158	}
156		159
157		160
158	/** Switch CPU to mode in which interrupts are serviced (currently it	161	/** Switch CPU to mode in which interrupts are serviced (currently it
159	* is Undefined mode).	162	* is Undefined mode).
160	*	163	*
161	* The default mode for interrupt servicing (Interrupt Mode)	164	* The default mode for interrupt servicing (Interrupt Mode)
162	* can not be used because of nested interrupts (which can occur	165	* can not be used because of nested interrupts (which can occur
163	* because interrupts are enabled in higher levels of interrupt handler).	166	* because interrupts are enabled in higher levels of interrupt handler).
164	*/	167	*/
165	inline static void switch_to_irq_servicing_mode()	168	inline static void switch_to_irq_servicing_mode()
166	{	169	{
167	/* switch to Undefined mode */	170	/* switch to Undefined mode */
168	asm volatile(	171	asm volatile(
169	/* save regs used during switching */	172	/* save regs used during switching */
170	"stmfd sp!, {r0-r3} \n"	173	"stmfd sp!, {r0-r3} \n"
171		174
172	/* save stack pointer and link register to r1, r2 */	175	/* save stack pointer and link register to r1, r2 */
173	"mov r1, sp \n"	176	"mov r1, sp \n"
174	"mov r2, lr \n"	177	"mov r2, lr \n"
175		178
176	/* mode switch */	179	/* mode switch */
177	"mrs r0, cpsr \n"	180	"mrs r0, cpsr \n"
178	"bic r0, r0, #0x1f \n"	181	"bic r0, r0, #0x1f \n"
179	"orr r0, r0, #0x1b \n"	182	"orr r0, r0, #0x1b \n"
180	"msr cpsr_c, r0 \n"	183	"msr cpsr_c, r0 \n"
181		184
182	/* restore saved sp and lr */	185	/* restore saved sp and lr */
183	"mov sp, r1 \n"	186	"mov sp, r1 \n"
184	"mov lr, r2 \n"	187	"mov lr, r2 \n"
185		188
186	/* restore original regs */	189	/* restore original regs */
187	"ldmfd sp!, {r0-r3} \n"	190	"ldmfd sp!, {r0-r3} \n"
188	);	191	);
189	}	192	}
190		193
191	/** Calls exception dispatch routine. */	194	/** Calls exception dispatch routine. */
192	#define CALL_EXC_DISPATCH(exception) \	195	#define CALL_EXC_DISPATCH(exception) \
-		196	asm volatile ( \
193	asm("mov r0, %0" : : "i" (exception)); \	197	"mov r0, %[exc]\n" \
194	asm("mov r1, r13"); \	198	"mov r1, r13\n" \
195	asm("bl exc_dispatch");	199	"bl exc_dispatch\n" \
-		200	:: [exc] "i" (exception) \
-		201	);\
196		202
197	/** General exception handler.	203	/** General exception handler.
198	*	204	*
199	* Stores registers, dispatches the exception,	205	* Stores registers, dispatches the exception,
200	* and finally restores registers and returns from exception processing.	206	* and finally restores registers and returns from exception processing.
201	*	207	*
202	* @param exception Exception number.	208	* @param exception Exception number.
203	*/	209	*/
204	#define PROCESS_EXCEPTION(exception) \	210	#define PROCESS_EXCEPTION(exception) \
205	setup_stack_and_save_regs(); \	211	setup_stack_and_save_regs(); \
206	CALL_EXC_DISPATCH(exception) \	212	CALL_EXC_DISPATCH(exception) \
207	load_regs();	213	load_regs();
208		214
209	/** Updates specified exception vector to jump to given handler.	215	/** Updates specified exception vector to jump to given handler.
210	*	216	*
211	* Addresses of handlers are stored in memory following exception vectors.	217	* Addresses of handlers are stored in memory following exception vectors.
212	*/	218	*/
213	static void install_handler(unsigned handler_addr, unsigned *vector)	219	static void install_handler(unsigned handler_addr, unsigned *vector)
214	{	220	{
215	/* relative address (related to exc. vector) of the word	221	/* relative address (related to exc. vector) of the word
216	* where handler's address is stored	222	* where handler's address is stored
217	*/	223	*/
218	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -	224	volatile uint32_t handler_address_ptr = EXC_VECTORS_SIZE -
219	PREFETCH_OFFSET;	225	PREFETCH_OFFSET;
220		226
221	/* make it LDR instruction and store at exception vector */	227	/* make it LDR instruction and store at exception vector */
222	*vector = handler_address_ptr \| LDR_OPCODE;	228	*vector = handler_address_ptr \| LDR_OPCODE;
223	smc_coherence(*vector);	229	smc_coherence(*vector);
224		230
225	/* store handler's address */	231	/* store handler's address */
226	*(vector + EXC_VECTORS) = handler_addr;	232	*(vector + EXC_VECTORS) = handler_addr;
227		233
228	}	234	}
229		235
230	/** Low-level Reset Exception handler. */	236	/** Low-level Reset Exception handler. */
231	static void reset_exception_entry(void)	237	static void reset_exception_entry(void)
232	{	238	{
233	PROCESS_EXCEPTION(EXC_RESET);	239	PROCESS_EXCEPTION(EXC_RESET);
234	}	240	}
235		241
236	/** Low-level Software Interrupt Exception handler. */	242	/** Low-level Software Interrupt Exception handler. */
237	static void swi_exception_entry(void)	243	static void swi_exception_entry(void)
238	{	244	{
239	PROCESS_EXCEPTION(EXC_SWI);	245	PROCESS_EXCEPTION(EXC_SWI);
240	}	246	}
241		247
242	/** Low-level Undefined Instruction Exception handler. */	248	/** Low-level Undefined Instruction Exception handler. */
243	static void undef_instr_exception_entry(void)	249	static void undef_instr_exception_entry(void)
244	{	250	{
245	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);	251	PROCESS_EXCEPTION(EXC_UNDEF_INSTR);
246	}	252	}
247		253
248	/** Low-level Fast Interrupt Exception handler. */	254	/** Low-level Fast Interrupt Exception handler. */
249	static void fiq_exception_entry(void)	255	static void fiq_exception_entry(void)
250	{	256	{
251	PROCESS_EXCEPTION(EXC_FIQ);	257	PROCESS_EXCEPTION(EXC_FIQ);
252	}	258	}
253		259
254	/** Low-level Prefetch Abort Exception handler. */	260	/** Low-level Prefetch Abort Exception handler. */
255	static void prefetch_abort_exception_entry(void)	261	static void prefetch_abort_exception_entry(void)
256	{	262	{
257	asm("sub lr, lr, #4");	263	asm("sub lr, lr, #4");
258	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);	264	PROCESS_EXCEPTION(EXC_PREFETCH_ABORT);
259	}	265	}
260		266
261	/** Low-level Data Abort Exception handler. */	267	/** Low-level Data Abort Exception handler. */
262	static void data_abort_exception_entry(void)	268	static void data_abort_exception_entry(void)
263	{	269	{
264	asm("sub lr, lr, #8");	270	asm("sub lr, lr, #8");
265	PROCESS_EXCEPTION(EXC_DATA_ABORT);	271	PROCESS_EXCEPTION(EXC_DATA_ABORT);
266	}	272	}
267		273
268	/** Low-level Interrupt Exception handler.	274	/** Low-level Interrupt Exception handler.
269	*	275	*
270	* CPU is switched to Undefined mode before further interrupt processing	276	* CPU is switched to Undefined mode before further interrupt processing
271	* because of possible occurence of nested interrupt exception, which	277	* because of possible occurence of nested interrupt exception, which
272	* would overwrite (and thus spoil) stack pointer.	278	* would overwrite (and thus spoil) stack pointer.
273	*/	279	*/
274	static void irq_exception_entry(void)	280	static void irq_exception_entry(void)
275	{	281	{
276	asm("sub lr, lr, #4");	282	asm("sub lr, lr, #4");
277	setup_stack_and_save_regs();	283	setup_stack_and_save_regs();
278		284
279	switch_to_irq_servicing_mode();	285	switch_to_irq_servicing_mode();
280		286
281	CALL_EXC_DISPATCH(EXC_IRQ)	287	CALL_EXC_DISPATCH(EXC_IRQ)
282		288
283	load_regs();	289	load_regs();
284	}	290	}
285		291
286	/** Software Interrupt handler.	292	/** Software Interrupt handler.
287	*	293	*
288	* Dispatches the syscall.	294	* Dispatches the syscall.
289	*/	295	*/
290	static void swi_exception(int exc_no, istate_t *istate)	296	static void swi_exception(int exc_no, istate_t *istate)
291	{	297	{
292	istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,	298	istate->r0 = syscall_handler(istate->r0, istate->r1, istate->r2,
293	istate->r3, istate->r4, istate->r5, istate->r6);	299	istate->r3, istate->r4, istate->r5, istate->r6);
294	}	300	}
295		301
296	/** Interrupt Exception handler.	302	/** Interrupt Exception handler.
297	*	303	*
298	* Determines the sources of interrupt and calls their handlers.	304	* Determines the sources of interrupt and calls their handlers.
299	*/	305	*/
300	static void irq_exception(int exc_no, istate_t *istate)	306	static void irq_exception(int exc_no, istate_t *istate)
301	{	307	{
302	machine_irq_exception(exc_no, istate);	308	machine_irq_exception(exc_no, istate);
303	}	309	}
304		310
305	/** Fills exception vectors with appropriate exception handlers. */	311	/** Fills exception vectors with appropriate exception handlers. */
306	void install_exception_handlers(void)	312	void install_exception_handlers(void)
307	{	313	{
308	install_handler((unsigned) reset_exception_entry,	314	install_handler((unsigned) reset_exception_entry,
309	(unsigned *) EXC_RESET_VEC);	315	(unsigned *) EXC_RESET_VEC);
310		316
311	install_handler((unsigned) undef_instr_exception_entry,	317	install_handler((unsigned) undef_instr_exception_entry,
312	(unsigned *) EXC_UNDEF_INSTR_VEC);	318	(unsigned *) EXC_UNDEF_INSTR_VEC);
313		319
314	install_handler((unsigned) swi_exception_entry,	320	install_handler((unsigned) swi_exception_entry,
315	(unsigned *) EXC_SWI_VEC);	321	(unsigned *) EXC_SWI_VEC);
316		322
317	install_handler((unsigned) prefetch_abort_exception_entry,	323	install_handler((unsigned) prefetch_abort_exception_entry,
318	(unsigned *) EXC_PREFETCH_ABORT_VEC);	324	(unsigned *) EXC_PREFETCH_ABORT_VEC);
319		325
320	install_handler((unsigned) data_abort_exception_entry,	326	install_handler((unsigned) data_abort_exception_entry,
321	(unsigned *) EXC_DATA_ABORT_VEC);	327	(unsigned *) EXC_DATA_ABORT_VEC);
322		328
323	install_handler((unsigned) irq_exception_entry,	329	install_handler((unsigned) irq_exception_entry,
324	(unsigned *) EXC_IRQ_VEC);	330	(unsigned *) EXC_IRQ_VEC);
325		331
326	install_handler((unsigned)fiq_exception_entry,	332	install_handler((unsigned)fiq_exception_entry,
327	(unsigned *) EXC_FIQ_VEC);	333	(unsigned *) EXC_FIQ_VEC);
328	}	334	}
329		335
330	#ifdef HIGH_EXCEPTION_VECTORS	336	#ifdef HIGH_EXCEPTION_VECTORS
331	/** Activates use of high exception vectors addresses. */	337	/** Activates use of high exception vectors addresses. */
332	static void high_vectors(void)	338	static void high_vectors(void)
333	{	339	{
334	uint32_t control_reg;	340	uint32_t control_reg;
335		341
-		342	asm volatile (
-		343	"mrc p15, 0, %[control_reg], c1, c1"
336	asm volatile("mrc p15, 0, %0, c1, c1" : "=r" (control_reg));	344	: [control_reg] "=r" (control_reg)
-		345	);
337		346
338	/* switch on the high vectors bit */	347	/* switch on the high vectors bit */
339	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;	348	control_reg \|= CP15_R1_HIGH_VECTORS_BIT;
340		349
-		350	asm volatile (
-		351	"mcr p15, 0, %[control_reg], c1, c1"
341	asm volatile("mcr p15, 0, %0, c1, c1" : : "r" (control_reg));	352	:: [control_reg] "r" (control_reg)
-		353	);
342	}	354	}
343	#endif	355	#endif
344		356
345	/** Initializes exception handling.	357	/** Initializes exception handling.
346	*	358	*
347	* Installs low-level exception handlers and then registers	359	* Installs low-level exception handlers and then registers
348	* exceptions and their handlers to kernel exception dispatcher.	360	* exceptions and their handlers to kernel exception dispatcher.
349	*/	361	*/
350	void exception_init(void)	362	void exception_init(void)
351	{	363	{
352	#ifdef HIGH_EXCEPTION_VECTORS	364	#ifdef HIGH_EXCEPTION_VECTORS
353	high_vectors();	365	high_vectors();
354	#endif	366	#endif
355	install_exception_handlers();	367	install_exception_handlers();
356		368
357	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);	369	exc_register(EXC_IRQ, "interrupt", (iroutine) irq_exception);
358	exc_register(EXC_PREFETCH_ABORT, "prefetch abort",	370	exc_register(EXC_PREFETCH_ABORT, "prefetch abort",
359	(iroutine) prefetch_abort);	371	(iroutine) prefetch_abort);
360	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);	372	exc_register(EXC_DATA_ABORT, "data abort", (iroutine) data_abort);
361	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);	373	exc_register(EXC_SWI, "software interrupt", (iroutine) swi_exception);
362	}	374	}
363		375
364	/** Prints #istate_t structure content.	376	/** Prints #istate_t structure content.
365	*	377	*
366	* @param istate Structure to be printed.	378	* @param istate Structure to be printed.
367	*/	379	*/
368	void print_istate(istate_t *istate)	380	void print_istate(istate_t *istate)
369	{	381	{
370	dprintf("istate dump:\n");	382	dprintf("istate dump:\n");
371		383
372	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",	384	dprintf(" r0: %x r1: %x r2: %x r3: %x\n",
373	istate->r0, istate->r1, istate->r2, istate->r3);	385	istate->r0, istate->r1, istate->r2, istate->r3);
374	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",	386	dprintf(" r4: %x r5: %x r6: %x r7: %x\n",
375	istate->r4, istate->r5, istate->r6, istate->r7);	387	istate->r4, istate->r5, istate->r6, istate->r7);
376	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",	388	dprintf(" r8: %x r8: %x r10: %x r11: %x\n",
377	istate->r8, istate->r9, istate->r10, istate->r11);	389	istate->r8, istate->r9, istate->r10, istate->r11);
378	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",	390	dprintf(" r12: %x sp: %x lr: %x spsr: %x\n",
379	istate->r12, istate->sp, istate->lr, istate->spsr);	391	istate->r12, istate->sp, istate->lr, istate->spsr);
380		392
381	dprintf(" pc: %x\n", istate->pc);	393	dprintf(" pc: %x\n", istate->pc);
382	}	394	}
383		395
384	/** @}	396	/** @}
385	*/	397	*/
386		398

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