WebSVN – HelenOS – Diff – /branches/dynload/kernel/arch/amd64/src/pm.c


/*
 * Copyright (c) 2008 Jakub Jermar
 * Copyright (c) 2005-2006 Ondrej Palkovsky
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions
 * are met:
 *
 * - Redistributions of source code must retain the above copyright
 *   notice, this list of conditions and the following disclaimer.
 * - Redistributions in binary form must reproduce the above copyright
 *   notice, this list of conditions and the following disclaimer in the
 *   documentation and/or other materials provided with the distribution.
 * - The name of the author may not be used to endorse or promote products
 *   derived from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
 
/** @addtogroup amd64  
 * @{
 */
/** @file
 */
 
#include <arch.h>
#include <arch/pm.h>
#include <arch/asm.h>
#include <mm/as.h>
#include <mm/frame.h>
#include <memstr.h>
#include <mm/slab.h>
 
/*
 * There is no segmentation in long mode so we set up flat mode. In this
 * mode, we use, for each privilege level, two segments spanning the
 * whole memory. One is for code and one is for data.
 */
 
descriptor_t gdt[GDT_ITEMS] = {
    /* NULL descriptor */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* KTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_KERNEL,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UDATA descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_DATA | AR_WRITABLE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* UTEXT descriptor */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_USER,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 1,
      .special     = 0,
      .granularity = 1,
      .base_24_31  = 0 },
    /* KTEXT 32-bit protected, for protected mode before long mode */
    { .limit_0_15  = 0xffff,
      .base_0_15   = 0,
      .base_16_23  = 0,
      .access      = AR_PRESENT | AR_CODE | DPL_KERNEL | AR_READABLE,
      .limit_16_19 = 0xf,
      .available   = 0,
      .longmode    = 0,
      .special     = 1,
      .granularity = 1,
      .base_24_31  = 0 },
    /* TSS descriptor - set up will be completed later,
     * on AMD64 it is 64-bit - 2 items in table */
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
    /* VESA Init descriptor */
#ifdef CONFIG_FB    
    { 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT | AR_CODE | DPL_KERNEL,
      0xf, 0, 0, 0, 0, 0
    }
#endif
};
 
idescriptor_t idt[IDT_ITEMS];
 
ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base = (uint64_t) gdt };
ptr_16_64_t idtr = {.limit = sizeof(idt), .base = (uint64_t) idt };
 
static tss_t tss;
tss_t *tss_p = NULL;
 
void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
{
    tss_descriptor_t *td = (tss_descriptor_t *) d;
 
    td->base_0_15 = base & 0xffff;
    td->base_16_23 = ((base) >> 16) & 0xff;
    td->base_24_31 = ((base) >> 24) & 0xff;
    td->base_32_63 = ((base) >> 32);
}
 
void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
{
    tss_descriptor_t *td = (tss_descriptor_t *) d;
   
    td->limit_0_15 = limit & 0xffff;
    td->limit_16_19 = (limit >> 16) & 0xf;
}
 
void idt_setoffset(idescriptor_t *d, uintptr_t offset)
{
    /*
     * Offset is a linear address.
     */
    d->offset_0_15 = offset & 0xffff;
    d->offset_16_31 = offset >> 16 & 0xffff;
    d->offset_32_63 = offset >> 32;
}
 
void tss_initialize(tss_t *t)
{
    memsetb(t, sizeof(tss_t), 0);
}
 
/*
 * This function takes care of proper setup of IDT and IDTR.
 */
void idt_init(void)
{
    idescriptor_t *d;
    int i;
 
    for (i = 0; i < IDT_ITEMS; i++) {
        d = &idt[i];
 
        d->unused = 0;
        d->selector = gdtselector(KTEXT_DES);
 
        d->present = 1;
        d->type = AR_INTERRUPT; /* masking interrupt */
 
        idt_setoffset(d, ((uintptr_t) interrupt_handlers) +
            i * interrupt_handler_size);
    }
}
 
/** Initialize segmentation - code/data/idt tables
 *
 */
void pm_init(void)
{
    descriptor_t *gdt_p = (descriptor_t *) gdtr.base;
    tss_descriptor_t *tss_desc;
   
    /*
     * Each CPU has its private GDT and TSS.
     * All CPUs share one IDT.
     */
   
    if (config.cpu_active == 1) {
        idt_init();
        /*
         * NOTE: bootstrap CPU has statically allocated TSS, because
         * the heap hasn't been initialized so far.
         */
        tss_p = &tss;
 
    } else {
        /* We are going to use malloc, which may return
         * non boot-mapped pointer, initialize the CR3 register
         * ahead of page_init */
        write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
       
        tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
        if (!tss_p)
            panic("Cannot allocate TSS.");
    }
   
    tss_initialize(tss_p);
   
    tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
    tss_desc->present = 1;
    tss_desc->type = AR_TSS;
    tss_desc->dpl = PL_KERNEL;
   
    gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
    gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
   
    gdtr_load(&gdtr);
    idtr_load(&idtr);
    /*
     * As of this moment, the current CPU has its own GDT pointing
     * to its own TSS. We just need to load the TR register.
     */
    tr_load(gdtselector(TSS_DES));
}
 
/* Reboot the machine by initiating
 * a triple fault
 */
void arch_reboot(void)
{
    preemption_disable();
    ipl_t ipl = interrupts_disable();
   
    memsetb(idt, sizeof(idt), 0);
    idtr_load(&idtr);
   
    interrupts_restore(ipl);
    asm volatile (
        "int $0x03\n"
        "cli\n"
        "hlt\n"
    );
}
 
/** @}
 */
 

Rev 4339	Rev 4346
1	/*	1	/*
2	* Copyright (c) 2008 Jakub Jermar	2	* Copyright (c) 2008 Jakub Jermar
3	* Copyright (c) 2005-2006 Ondrej Palkovsky	3	* Copyright (c) 2005-2006 Ondrej Palkovsky
4	* All rights reserved.	4	* All rights reserved.
5	*	5	*
6	* Redistribution and use in source and binary forms, with or without	6	* Redistribution and use in source and binary forms, with or without
7	* modification, are permitted provided that the following conditions	7	* modification, are permitted provided that the following conditions
8	* are met:	8	* are met:
9	*	9	*
10	* - Redistributions of source code must retain the above copyright	10	* - Redistributions of source code must retain the above copyright
11	* notice, this list of conditions and the following disclaimer.	11	* notice, this list of conditions and the following disclaimer.
12	* - Redistributions in binary form must reproduce the above copyright	12	* - Redistributions in binary form must reproduce the above copyright
13	* notice, this list of conditions and the following disclaimer in the	13	* notice, this list of conditions and the following disclaimer in the
14	* documentation and/or other materials provided with the distribution.	14	* documentation and/or other materials provided with the distribution.
15	* - The name of the author may not be used to endorse or promote products	15	* - The name of the author may not be used to endorse or promote products
16	* derived from this software without specific prior written permission.	16	* derived from this software without specific prior written permission.
17	*	17	*
18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	18	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	19	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.	20	* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,	21	* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT	22	* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,	23	* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY	24	* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT	25	* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF	26	* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.	27	* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28	*/	28	*/
29		29
30	/** @addtogroup amd64	30	/** @addtogroup amd64
31	* @{	31	* @{
32	*/	32	*/
33	/** @file	33	/** @file
34	*/	34	*/
35		35
36	#include <arch.h>	36	#include <arch.h>
37	#include <arch/pm.h>	37	#include <arch/pm.h>
38	#include <arch/asm.h>	38	#include <arch/asm.h>
39	#include <mm/as.h>	39	#include <mm/as.h>
40	#include <mm/frame.h>	40	#include <mm/frame.h>
41	#include <memstr.h>	41	#include <memstr.h>
42	#include <mm/slab.h>	42	#include <mm/slab.h>
43		43
44	/*	44	/*
45	* There is no segmentation in long mode so we set up flat mode. In this	45	* There is no segmentation in long mode so we set up flat mode. In this
46	* mode, we use, for each privilege level, two segments spanning the	46	* mode, we use, for each privilege level, two segments spanning the
47	* whole memory. One is for code and one is for data.	47	* whole memory. One is for code and one is for data.
48	*/	48	*/
49		49
50	descriptor_t gdt[GDT_ITEMS] = {	50	descriptor_t gdt[GDT_ITEMS] = {
51	/* NULL descriptor */	51	/* NULL descriptor */
52	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	52	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
53	/* KTEXT descriptor */	53	/* KTEXT descriptor */
54	{ .limit_0_15 = 0xffff,	54	{ .limit_0_15 = 0xffff,
55	.base_0_15 = 0,	55	.base_0_15 = 0,
56	.base_16_23 = 0,	56	.base_16_23 = 0,
57	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,	57	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,
58	.limit_16_19 = 0xf,	58	.limit_16_19 = 0xf,
59	.available = 0,	59	.available = 0,
60	.longmode = 1,	60	.longmode = 1,
61	.special = 0,	61	.special = 0,
62	.granularity = 1,	62	.granularity = 1,
63	.base_24_31 = 0 },	63	.base_24_31 = 0 },
64	/* KDATA descriptor */	64	/* KDATA descriptor */
65	{ .limit_0_15 = 0xffff,	65	{ .limit_0_15 = 0xffff,
66	.base_0_15 = 0,	66	.base_0_15 = 0,
67	.base_16_23 = 0,	67	.base_16_23 = 0,
68	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,	68	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_KERNEL,
69	.limit_16_19 = 0xf,	69	.limit_16_19 = 0xf,
70	.available = 0,	70	.available = 0,
71	.longmode = 0,	71	.longmode = 0,
72	.special = 0,	72	.special = 0,
73	.granularity = 1,	73	.granularity = 1,
74	.base_24_31 = 0 },	74	.base_24_31 = 0 },
75	/* UDATA descriptor */	75	/* UDATA descriptor */
76	{ .limit_0_15 = 0xffff,	76	{ .limit_0_15 = 0xffff,
77	.base_0_15 = 0,	77	.base_0_15 = 0,
78	.base_16_23 = 0,	78	.base_16_23 = 0,
79	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,	79	.access = AR_PRESENT \| AR_DATA \| AR_WRITABLE \| DPL_USER,
80	.limit_16_19 = 0xf,	80	.limit_16_19 = 0xf,
81	.available = 0,	81	.available = 0,
82	.longmode = 0,	82	.longmode = 0,
83	.special = 1,	83	.special = 1,
84	.granularity = 1,	84	.granularity = 1,
85	.base_24_31 = 0 },	85	.base_24_31 = 0 },
86	/* UTEXT descriptor */	86	/* UTEXT descriptor */
87	{ .limit_0_15 = 0xffff,	87	{ .limit_0_15 = 0xffff,
88	.base_0_15 = 0,	88	.base_0_15 = 0,
89	.base_16_23 = 0,	89	.base_16_23 = 0,
90	.access = AR_PRESENT \| AR_CODE \| DPL_USER,	90	.access = AR_PRESENT \| AR_CODE \| DPL_USER,
91	.limit_16_19 = 0xf,	91	.limit_16_19 = 0xf,
92	.available = 0,	92	.available = 0,
93	.longmode = 1,	93	.longmode = 1,
94	.special = 0,	94	.special = 0,
95	.granularity = 1,	95	.granularity = 1,
96	.base_24_31 = 0 },	96	.base_24_31 = 0 },
97	/* KTEXT 32-bit protected, for protected mode before long mode */	97	/* KTEXT 32-bit protected, for protected mode before long mode */
98	{ .limit_0_15 = 0xffff,	98	{ .limit_0_15 = 0xffff,
99	.base_0_15 = 0,	99	.base_0_15 = 0,
100	.base_16_23 = 0,	100	.base_16_23 = 0,
101	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,	101	.access = AR_PRESENT \| AR_CODE \| DPL_KERNEL \| AR_READABLE,
102	.limit_16_19 = 0xf,	102	.limit_16_19 = 0xf,
103	.available = 0,	103	.available = 0,
104	.longmode = 0,	104	.longmode = 0,
105	.special = 1,	105	.special = 1,
106	.granularity = 1,	106	.granularity = 1,
107	.base_24_31 = 0 },	107	.base_24_31 = 0 },
108	/* TSS descriptor - set up will be completed later,	108	/* TSS descriptor - set up will be completed later,
109	* on AMD64 it is 64-bit - 2 items in table */	109	* on AMD64 it is 64-bit - 2 items in table */
110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	110	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
111	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },	111	{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
112	/* VESA Init descriptor */	112	/* VESA Init descriptor */
113	#ifdef CONFIG_FB	113	#ifdef CONFIG_FB
114	{ 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT \| AR_CODE \| DPL_KERNEL,	114	{ 0xffff, 0, VESA_INIT_SEGMENT >> 12, AR_PRESENT \| AR_CODE \| DPL_KERNEL,
115	0xf, 0, 0, 0, 0, 0	115	0xf, 0, 0, 0, 0, 0
116	}	116	}
117	#endif	117	#endif
118	};	118	};
119		119
120	idescriptor_t idt[IDT_ITEMS];	120	idescriptor_t idt[IDT_ITEMS];
121		121
122	ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base = (uint64_t) gdt };	122	ptr_16_64_t gdtr = {.limit = sizeof(gdt), .base = (uint64_t) gdt };
123	ptr_16_64_t idtr = {.limit = sizeof(idt), .base = (uint64_t) idt };	123	ptr_16_64_t idtr = {.limit = sizeof(idt), .base = (uint64_t) idt };
124		124
125	static tss_t tss;	125	static tss_t tss;
126	tss_t *tss_p = NULL;	126	tss_t *tss_p = NULL;
127		127
128	void gdt_tss_setbase(descriptor_t *d, uintptr_t base)	128	void gdt_tss_setbase(descriptor_t *d, uintptr_t base)
129	{	129	{
130	tss_descriptor_t td = (tss_descriptor_t ) d;	130	tss_descriptor_t td = (tss_descriptor_t ) d;
131		131
132	td->base_0_15 = base & 0xffff;	132	td->base_0_15 = base & 0xffff;
133	td->base_16_23 = ((base) >> 16) & 0xff;	133	td->base_16_23 = ((base) >> 16) & 0xff;
134	td->base_24_31 = ((base) >> 24) & 0xff;	134	td->base_24_31 = ((base) >> 24) & 0xff;
135	td->base_32_63 = ((base) >> 32);	135	td->base_32_63 = ((base) >> 32);
136	}	136	}
137		137
138	void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)	138	void gdt_tss_setlimit(descriptor_t *d, uint32_t limit)
139	{	139	{
140	struct tss_descriptor td = (tss_descriptor_t ) d;	140	tss_descriptor_t td = (tss_descriptor_t ) d;
141		141
142	td->limit_0_15 = limit & 0xffff;	142	td->limit_0_15 = limit & 0xffff;
143	td->limit_16_19 = (limit >> 16) & 0xf;	143	td->limit_16_19 = (limit >> 16) & 0xf;
144	}	144	}
145		145
146	void idt_setoffset(idescriptor_t *d, uintptr_t offset)	146	void idt_setoffset(idescriptor_t *d, uintptr_t offset)
147	{	147	{
148	/*	148	/*
149	* Offset is a linear address.	149	* Offset is a linear address.
150	*/	150	*/
151	d->offset_0_15 = offset & 0xffff;	151	d->offset_0_15 = offset & 0xffff;
152	d->offset_16_31 = offset >> 16 & 0xffff;	152	d->offset_16_31 = offset >> 16 & 0xffff;
153	d->offset_32_63 = offset >> 32;	153	d->offset_32_63 = offset >> 32;
154	}	154	}
155		155
156	void tss_initialize(tss_t *t)	156	void tss_initialize(tss_t *t)
157	{	157	{
158	memsetb(t, sizeof(tss_t), 0);	158	memsetb(t, sizeof(tss_t), 0);
159	}	159	}
160		160
161	/*	161	/*
162	* This function takes care of proper setup of IDT and IDTR.	162	* This function takes care of proper setup of IDT and IDTR.
163	*/	163	*/
164	void idt_init(void)	164	void idt_init(void)
165	{	165	{
166	idescriptor_t *d;	166	idescriptor_t *d;
167	int i;	167	int i;
168		168
169	for (i = 0; i < IDT_ITEMS; i++) {	169	for (i = 0; i < IDT_ITEMS; i++) {
170	d = &idt[i];	170	d = &idt[i];
171		171
172	d->unused = 0;	172	d->unused = 0;
173	d->selector = gdtselector(KTEXT_DES);	173	d->selector = gdtselector(KTEXT_DES);
174		174
175	d->present = 1;	175	d->present = 1;
176	d->type = AR_INTERRUPT; /* masking interrupt */	176	d->type = AR_INTERRUPT; /* masking interrupt */
177		177
178	idt_setoffset(d, ((uintptr_t) interrupt_handlers) +	178	idt_setoffset(d, ((uintptr_t) interrupt_handlers) +
179	i * interrupt_handler_size);	179	i * interrupt_handler_size);
180	}	180	}
181	}	181	}
182		182
183	/** Initialize segmentation - code/data/idt tables	183	/** Initialize segmentation - code/data/idt tables
184	*	184	*
185	*/	185	*/
186	void pm_init(void)	186	void pm_init(void)
187	{	187	{
188	descriptor_t gdt_p = (struct descriptor ) gdtr.base;	188	descriptor_t gdt_p = (descriptor_t ) gdtr.base;
189	tss_descriptor_t *tss_desc;	189	tss_descriptor_t *tss_desc;
190		190
191	/*	191	/*
192	* Each CPU has its private GDT and TSS.	192	* Each CPU has its private GDT and TSS.
193	* All CPUs share one IDT.	193	* All CPUs share one IDT.
194	*/	194	*/
195		195
196	if (config.cpu_active == 1) {	196	if (config.cpu_active == 1) {
197	idt_init();	197	idt_init();
198	/*	198	/*
199	* NOTE: bootstrap CPU has statically allocated TSS, because	199	* NOTE: bootstrap CPU has statically allocated TSS, because
200	* the heap hasn't been initialized so far.	200	* the heap hasn't been initialized so far.
201	*/	201	*/
202	tss_p = &tss;	202	tss_p = &tss;
203	}	-
204	else {	203	} else {
205	/* We are going to use malloc, which may return	204	/* We are going to use malloc, which may return
206	* non boot-mapped pointer, initialize the CR3 register	205	* non boot-mapped pointer, initialize the CR3 register
207	* ahead of page_init */	206	* ahead of page_init */
208	write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);	207	write_cr3((uintptr_t) AS_KERNEL->genarch.page_table);
209		208
210	tss_p = (struct tss *) malloc(sizeof(tss_t), FRAME_ATOMIC);	209	tss_p = (tss_t *) malloc(sizeof(tss_t), FRAME_ATOMIC);
211	if (!tss_p)	210	if (!tss_p)
212	panic("Cannot allocate TSS.");	211	panic("Cannot allocate TSS.");
213	}	212	}
214		213
215	tss_initialize(tss_p);	214	tss_initialize(tss_p);
216		215
217	tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);	216	tss_desc = (tss_descriptor_t *) (&gdt_p[TSS_DES]);
218	tss_desc->present = 1;	217	tss_desc->present = 1;
219	tss_desc->type = AR_TSS;	218	tss_desc->type = AR_TSS;
220	tss_desc->dpl = PL_KERNEL;	219	tss_desc->dpl = PL_KERNEL;
221		220
222	gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);	221	gdt_tss_setbase(&gdt_p[TSS_DES], (uintptr_t) tss_p);
223	gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);	222	gdt_tss_setlimit(&gdt_p[TSS_DES], TSS_BASIC_SIZE - 1);
224		223
225	gdtr_load(&gdtr);	224	gdtr_load(&gdtr);
226	idtr_load(&idtr);	225	idtr_load(&idtr);
227	/*	226	/*
228	* As of this moment, the current CPU has its own GDT pointing	227	* As of this moment, the current CPU has its own GDT pointing
229	* to its own TSS. We just need to load the TR register.	228	* to its own TSS. We just need to load the TR register.
230	*/	229	*/
231	tr_load(gdtselector(TSS_DES));	230	tr_load(gdtselector(TSS_DES));
232	}	231	}
233		232
234	/* Reboot the machine by initiating	233	/* Reboot the machine by initiating
235	* a triple fault	234	* a triple fault
236	*/	235	*/
237	void arch_reboot(void)	236	void arch_reboot(void)
238	{	237	{
239	preemption_disable();	238	preemption_disable();
240	ipl_t ipl = interrupts_disable();	239	ipl_t ipl = interrupts_disable();
241		240
242	memsetb(idt, sizeof(idt), 0);	241	memsetb(idt, sizeof(idt), 0);
243	idtr_load(&idtr);	242	idtr_load(&idtr);
244		243
245	interrupts_restore(ipl);	244	interrupts_restore(ipl);
246	asm volatile (	245	asm volatile (
247	"int $0x03\n"	246	"int $0x03\n"
248	"cli\n"	247	"cli\n"
249	"hlt\n"	248	"hlt\n"
250	);	249	);
251	}	250	}
252		251
253	/** @}	252	/** @}
254	*/	253	*/
255		254

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(root)/branches/dynload/kernel/arch/amd64/src/pm.c – Rev 4339 → 4346