Subversion Repositories HelenOS

Rev

Rev 3022 | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 3022 Rev 4055
Line 33... Line 33...
33
 */
33
 */
34
 
34
 
35
#ifndef KERN_sparc64_MMU_H_
35
#ifndef KERN_sparc64_MMU_H_
36
#define KERN_sparc64_MMU_H_
36
#define KERN_sparc64_MMU_H_
37
 
37
 
-
 
38
#if defined(US)
38
/* LSU Control Register ASI. */
39
/* LSU Control Register ASI. */
39
#define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
40
#define ASI_LSU_CONTROL_REG     0x45    /**< Load/Store Unit Control Register. */
-
 
41
#endif
40
 
42
 
41
/* I-MMU ASIs. */
43
/* I-MMU ASIs. */
42
#define ASI_IMMU            0x50
44
#define ASI_IMMU            0x50
43
#define ASI_IMMU_TSB_8KB_PTR_REG    0x51    
45
#define ASI_IMMU_TSB_8KB_PTR_REG    0x51    
44
#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
46
#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
Line 50... Line 52...
50
/* Virtual Addresses within ASI_IMMU. */
52
/* Virtual Addresses within ASI_IMMU. */
51
#define VA_IMMU_TSB_TAG_TARGET      0x0 /**< IMMU TSB tag target register. */
53
#define VA_IMMU_TSB_TAG_TARGET      0x0 /**< IMMU TSB tag target register. */
52
#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
54
#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
53
#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
55
#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
54
#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
56
#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
-
 
57
#if defined (US3)
-
 
58
#define VA_IMMU_PRIMARY_EXTENSION   0x48    /**< IMMU TSB primary extension register */
-
 
59
#define VA_IMMU_NUCLEUS_EXTENSION   0x58    /**< IMMU TSB nucleus extension register */
-
 
60
#endif
-
 
61
 
55
 
62
 
56
/* D-MMU ASIs. */
63
/* D-MMU ASIs. */
57
#define ASI_DMMU            0x58
64
#define ASI_DMMU            0x58
58
#define ASI_DMMU_TSB_8KB_PTR_REG    0x59    
65
#define ASI_DMMU_TSB_8KB_PTR_REG    0x59    
59
#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
66
#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
Line 71... Line 78...
71
#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
78
#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
72
#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
79
#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
73
#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
80
#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
74
#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
81
#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
75
#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
82
#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
-
 
83
#if defined (US3)
-
 
84
#define VA_DMMU_PRIMARY_EXTENSION   0x48    /**< DMMU TSB primary extension register */
-
 
85
#define VA_DMMU_SECONDARY_EXTENSION 0x50    /**< DMMU TSB secondary extension register */
-
 
86
#define VA_DMMU_NUCLEUS_EXTENSION   0x58    /**< DMMU TSB nucleus extension register */
-
 
87
#endif
76
 
88
 
77
#ifndef __ASM__
89
#ifndef __ASM__
78
 
90
 
79
#include <arch/asm.h>
91
#include <arch/asm.h>
80
#include <arch/barrier.h>
92
#include <arch/barrier.h>
81
#include <arch/types.h>
93
#include <arch/types.h>
82
 
94
 
-
 
95
#if defined(US)
83
/** LSU Control Register. */
96
/** LSU Control Register. */
84
typedef union {
97
typedef union {
85
    uint64_t value;
98
    uint64_t value;
86
    struct {
99
    struct {
87
        unsigned : 23;
100
        unsigned : 23;
Line 98... Line 111...
98
        unsigned dc : 1;    /**< D-Cache enable. */
111
        unsigned dc : 1;    /**< D-Cache enable. */
99
        unsigned ic : 1;    /**< I-Cache enable. */
112
        unsigned ic : 1;    /**< I-Cache enable. */
100
       
113
       
101
    } __attribute__ ((packed));
114
    } __attribute__ ((packed));
102
} lsu_cr_reg_t;
115
} lsu_cr_reg_t;
-
 
116
#endif /* US */
103
 
117
 
104
#endif /* !def __ASM__ */
118
#endif /* !def __ASM__ */
105
 
119
 
106
#endif
120
#endif
107
 
121