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| Rev 3022 | Rev 4055 | ||
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| Line 38... | Line 38... | ||
| 38 | #include <arch/mm/page_fault.h> |
38 | #include <arch/mm/page_fault.h> |
| 39 | #include <mm/as.h> |
39 | #include <mm/as.h> |
| 40 | #include <genarch/mm/page_pt.h> |
40 | #include <genarch/mm/page_pt.h> |
| 41 | #include <arch.h> |
41 | #include <arch.h> |
| 42 | #include <interrupt.h> |
42 | #include <interrupt.h> |
| - | 43 | #include <print.h> |
|
| 43 | 44 | ||
| 44 | /** Returns value stored in fault status register. |
45 | /** Returns value stored in fault status register. |
| 45 | * |
46 | * |
| 46 | * @return Value stored in CP15 fault status register (FSR). |
47 | * @return Value stored in CP15 fault status register (FSR). |
| 47 | */ |
48 | */ |
| 48 | static inline fault_status_t read_fault_status_register(void) |
49 | static inline fault_status_t read_fault_status_register(void) |
| 49 | { |
50 | { |
| 50 | fault_status_union_t fsu; |
51 | fault_status_union_t fsu; |
| 51 | 52 | ||
| 52 | /* fault status is stored in CP15 register 5 */ |
53 | /* fault status is stored in CP15 register 5 */ |
| 53 | asm volatile ( |
54 | asm volatile ( |
| 54 | "mrc p15, 0, %0, c5, c0, 0" |
55 | "mrc p15, 0, %[dummy], c5, c0, 0" |
| 55 | : "=r"(fsu.dummy) |
56 | : [dummy] "=r" (fsu.dummy) |
| 56 | ); |
57 | ); |
| - | 58 | ||
| 57 | return fsu.fs; |
59 | return fsu.fs; |
| 58 | } |
60 | } |
| 59 | 61 | ||
| 60 | /** Returns FAR (fault address register) content. |
62 | /** Returns FAR (fault address register) content. |
| 61 | * |
63 | * |
| 62 | * @return FAR (fault address register) content (address that caused a page |
64 | * @return FAR (fault address register) content (address that caused a page |
| 63 | * fault) |
65 | * fault) |
| 64 | */ |
66 | */ |
| 65 | static inline uintptr_t read_fault_address_register(void) |
67 | static inline uintptr_t read_fault_address_register(void) |
| 66 | { |
68 | { |
| 67 | uintptr_t ret; |
69 | uintptr_t ret; |
| 68 | 70 | ||
| 69 | /* fault adress is stored in CP15 register 6 */ |
71 | /* fault adress is stored in CP15 register 6 */ |
| 70 | asm volatile ( |
72 | asm volatile ( |
| 71 | "mrc p15, 0, %0, c6, c0, 0" |
73 | "mrc p15, 0, %[ret], c6, c0, 0" |
| 72 | : "=r"(ret) |
74 | : [ret] "=r" (ret) |
| 73 | ); |
75 | ); |
| - | 76 | ||
| 74 | return ret; |
77 | return ret; |
| 75 | } |
78 | } |
| 76 | 79 | ||
| 77 | /** Decides whether the instruction is load/store or not. |
80 | /** Decides whether the instruction is load/store or not. |
| 78 | * |
81 | * |
| 79 | * @param instr Instruction |
82 | * @param instr Instruction |
| 80 | * |
83 | * |
| 81 | * @return true when instruction is load/store, false otherwise |
84 | * @return true when instruction is load/store, false otherwise |
| - | 85 | * |
|
| 82 | */ |
86 | */ |
| 83 | static inline bool is_load_store_instruction(instruction_t instr) |
87 | static inline bool is_load_store_instruction(instruction_t instr) |
| 84 | { |
88 | { |
| 85 | /* load store immediate offset */ |
89 | /* load store immediate offset */ |
| 86 | if (instr.type == 0x2) { |
90 | if (instr.type == 0x2) |
| 87 | return true; |
91 | return true; |
| 88 | } |
92 | |
| 89 | - | ||
| 90 | /* load store register offset */ |
93 | /* load store register offset */ |
| 91 | if (instr.type == 0x3 && instr.bit4 == 0) { |
94 | if ((instr.type == 0x3) && (instr.bit4 == 0)) |
| 92 | return true; |
95 | return true; |
| 93 | } |
96 | |
| 94 | - | ||
| 95 | /* load store multiple */ |
97 | /* load store multiple */ |
| 96 | if (instr.type == 0x4) { |
98 | if (instr.type == 0x4) |
| 97 | return true; |
99 | return true; |
| 98 | } |
100 | |
| 99 | - | ||
| 100 | /* oprocessor load/store */ |
101 | /* oprocessor load/store */ |
| 101 | if (instr.type == 0x6) { |
102 | if (instr.type == 0x6) |
| 102 | return true; |
103 | return true; |
| 103 | } |
104 | |
| 104 | - | ||
| 105 | return false; |
105 | return false; |
| 106 | } |
106 | } |
| 107 | 107 | ||
| 108 | /** Decides whether the instruction is swap or not. |
108 | /** Decides whether the instruction is swap or not. |
| 109 | * |
109 | * |
| Line 112... | Line 112... | ||
| 112 | * @return true when instruction is swap, false otherwise |
112 | * @return true when instruction is swap, false otherwise |
| 113 | */ |
113 | */ |
| 114 | static inline bool is_swap_instruction(instruction_t instr) |
114 | static inline bool is_swap_instruction(instruction_t instr) |
| 115 | { |
115 | { |
| 116 | /* swap, swapb instruction */ |
116 | /* swap, swapb instruction */ |
| 117 | if (instr.type == 0x0 && |
117 | if ((instr.type == 0x0) && |
| 118 | (instr.opcode == 0x8 || instr.opcode == 0xa) && |
118 | ((instr.opcode == 0x8) || (instr.opcode == 0xa)) && |
| 119 | instr.access == 0x0 && instr.bits567 == 0x4 && instr.bit4 == 1) { |
119 | (instr.access == 0x0) && (instr.bits567 == 0x4) && (instr.bit4 == 1)) |
| 120 | return true; |
120 | return true; |
| 121 | } |
121 | |
| 122 | - | ||
| 123 | return false; |
122 | return false; |
| 124 | } |
123 | } |
| 125 | 124 | ||
| 126 | /** Decides whether read or write into memory is requested. |
125 | /** Decides whether read or write into memory is requested. |
| 127 | * |
126 | * |
| Line 139... | Line 138... | ||
| 139 | 138 | ||
| 140 | instruction_t instr = *(instr_union.instr); |
139 | instruction_t instr = *(instr_union.instr); |
| 141 | 140 | ||
| 142 | /* undefined instructions */ |
141 | /* undefined instructions */ |
| 143 | if (instr.condition == 0xf) { |
142 | if (instr.condition == 0xf) { |
| 144 | panic("page_fault - instruction doesn't access memory " |
143 | panic("page_fault - instruction does not access memory " |
| 145 | "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
144 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
| 146 | return PF_ACCESS_EXEC; |
145 | return PF_ACCESS_EXEC; |
| 147 | } |
146 | } |
| 148 | 147 | ||
| 149 | /* load store instructions */ |
148 | /* load store instructions */ |
| 150 | if (is_load_store_instruction(instr)) { |
149 | if (is_load_store_instruction(instr)) { |
| Line 159... | Line 158... | ||
| 159 | if (is_swap_instruction(instr)) { |
158 | if (is_swap_instruction(instr)) { |
| 160 | return PF_ACCESS_WRITE; |
159 | return PF_ACCESS_WRITE; |
| 161 | } |
160 | } |
| 162 | 161 | ||
| 163 | panic("page_fault - instruction doesn't access memory " |
162 | panic("page_fault - instruction doesn't access memory " |
| 164 | "(instr_code: %x, badvaddr:%x)", instr, badvaddr); |
163 | "(instr_code: %x, badvaddr:%x).", instr, badvaddr); |
| 165 | 164 | ||
| 166 | return PF_ACCESS_EXEC; |
165 | return PF_ACCESS_EXEC; |
| 167 | } |
166 | } |
| 168 | 167 | ||
| 169 | /** Handles "data abort" exception (load or store at invalid address). |
168 | /** Handles "data abort" exception (load or store at invalid address). |
| Line 185... | Line 184... | ||
| 185 | print_istate(istate); |
184 | print_istate(istate); |
| 186 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), " |
185 | dprintf("page fault - pc: %x, va: %x, status: %x(%x), " |
| 187 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
186 | "access:%d\n", istate->pc, badvaddr, fsr.status, fsr, |
| 188 | access); |
187 | access); |
| 189 | 188 | ||
| 190 | fault_if_from_uspace(istate, "Page fault: %#x", badvaddr); |
189 | fault_if_from_uspace(istate, "Page fault: %#x.", badvaddr); |
| 191 | panic("page fault\n"); |
190 | panic("Page fault."); |
| 192 | } |
191 | } |
| 193 | } |
192 | } |
| 194 | 193 | ||
| 195 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
194 | /** Handles "prefetch abort" exception (instruction couldn't be executed). |
| 196 | * |
195 | * |
| Line 202... | Line 201... | ||
| 202 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
201 | int ret = as_page_fault(istate->pc, PF_ACCESS_EXEC, istate); |
| 203 | 202 | ||
| 204 | if (ret == AS_PF_FAULT) { |
203 | if (ret == AS_PF_FAULT) { |
| 205 | dprintf("prefetch_abort\n"); |
204 | dprintf("prefetch_abort\n"); |
| 206 | print_istate(istate); |
205 | print_istate(istate); |
| 207 | panic("page fault - prefetch_abort at address: %x\n", |
206 | panic("page fault - prefetch_abort at address: %x.", |
| 208 | istate->pc); |
207 | istate->pc); |
| 209 | } |
208 | } |
| 210 | } |
209 | } |
| 211 | 210 | ||
| 212 | /** @} |
211 | /** @} |