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Rev 3529 Rev 3759
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#define QEMU_ICP_HALT_OFFSET         0x10
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#define QEMU_ICP_HALT_OFFSET         0x10
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#define QEMU_ICP_RTC                 0x13000000
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#define QEMU_ICP_RTC                 0x13000000
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#define QEMU_ICP_RTC_FREQ_OFFSET     0x100
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#define QEMU_ICP_RTC_FREQ_OFFSET     0x100
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#define QEMU_ICP_RTC_ACK_OFFSET      0x110
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#define QEMU_ICP_RTC_ACK_OFFSET      0x110
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#define QEMU_ICP_IRQC                0x14000000
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#define QEMU_ICP_IRQC                0x14000000
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#define QEMU_ICP_IRQC_MASK_OFFSET    0x8
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#define QEMU_ICP_IRQC_MASK_OFFSET    0xC
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#define QEMU_ICP_IRQC_UNMASK_OFFSET  0xC
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#define QEMU_ICP_IRQC_UNMASK_OFFSET  0x8
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#define QEMU_ICP_MP                  0x11000000
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#define QEMU_ICP_MP                  0x11000000
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#define QEMU_ICP_MP_MEMSIZE_OFFSET   0x0090
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#define QEMU_ICP_MP_MEMSIZE_OFFSET   0x0090
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#define QEMU_ICP_FB                  0x94000
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#define QEMU_ICP_FB                  0x94000
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#define ICP_VGA              0xC0000000
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#define ICP_VGA              0xC0000000
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#define ICP_CMCR             0x10000000
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#define ICP_CMCR             0x10000000
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/* IRQs */
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/* IRQs */
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#define QEMU_ICP_KBD_IRQ        3
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#define QEMU_ICP_KBD_IRQ        0x03
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#define QEMU_ICP_TIMER_IRQ  5
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#define QEMU_ICP_TIMER_IRQ      0x05
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static qemu_icp_hw_map_t qemu_icp_hw_map;
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static qemu_icp_hw_map_t qemu_icp_hw_map;
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static chardev_t console;
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static chardev_t console;
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static irq_t qemu_icp_console_irq;
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static irq_t qemu_icp_console_irq;
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static irq_t qemu_icp_timer_irq;
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static irq_t qemu_icp_timer_irq;
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 *
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 *
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 * @param irq interrupt number
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 * @param irq interrupt number
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 */
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 */
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static inline void qemu_icp_irqc_unmask(uint32_t irq)
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static inline void qemu_icp_irqc_unmask(uint32_t irq)
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{
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{
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    *((uint32_t *) qemu_icp_hw_map.irqc_unmask) = irq;
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    *((uint32_t *) qemu_icp_hw_map.irqc_unmask) |= irq;
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}
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}
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/** Initializes the icp frame buffer */
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/** Initializes the icp frame buffer */
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void qemu_icp_fb_init(void)
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void qemu_icp_fb_init(void)
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{
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{