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 */
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 */
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#ifndef KERN_arm32_REGUTILS_H_
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#ifndef KERN_arm32_REGUTILS_H_
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#define KERN_arm32_REGUTILS_H_
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#define KERN_arm32_REGUTILS_H_
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#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)
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#define STATUS_REG_IRQ_DISABLED_BIT (1 << 7)
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#define STATUS_REG_MODE_MASK        0x1f
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#define STATUS_REG_MODE_MASK        0x1f
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#define CP15_R1_HIGH_VECTORS_BIT    (1 << 13)
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#define CP15_R1_HIGH_VECTORS_BIT    (1 << 13)
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#define SUPERVISOR_MODE   0x13
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#define SUPERVISOR_MODE   0x13
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#define ABORT_MODE        0x17
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#define ABORT_MODE        0x17
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#define UNDEFINED_MODE    0x1b
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#define UNDEFINED_MODE    0x1b
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#define SYSTEM_MODE       0x1f
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#define SYSTEM_MODE       0x1f
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/* [CS]PRS manipulation macros */
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/* [CS]PRS manipulation macros */
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#define GEN_STATUS_READ(nm,reg) \
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#define GEN_STATUS_READ(nm,reg) \
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  static inline uint32_t nm## _status_reg_read(void) \
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static inline uint32_t nm## _status_reg_read(void) \
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  { \
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{ \
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      uint32_t retval; \
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    uint32_t retval; \
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      asm volatile("mrs %0, " #reg : "=r"(retval)); \
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    asm volatile("mrs %0, " #reg : "=r" (retval)); \
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      return retval; \
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    return retval; \
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  }
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}
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#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
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#define GEN_STATUS_WRITE(nm,reg,fieldname, field) \
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  static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
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static inline void nm## _status_reg_ ##fieldname## _write(uint32_t value) \
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  { \
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{ \
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      asm volatile("msr " #reg "_" #field ", %0" : : "r"(value)); \
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    asm volatile("msr " #reg "_" #field ", %0" : : "r" (value)); \
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  }
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}
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/** Returns the value of CPSR (Current Program Status Register). */
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/** Returns the value of CPSR (Current Program Status Register). */
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GEN_STATUS_READ(current, cpsr)
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GEN_STATUS_READ(current, cpsr)
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