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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#
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#
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#include <arch/stack.h>
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#define STACK_ITEMS		12
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#define STACK_FRAME_SIZE	((STACK_ITEMS*STACK_ITEM_SIZE) + STACK_SCRATCH_AREA_SIZE)
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#if (STACK_FRAME_SIZE % STACK_ALIGNMENT != 0)
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#error Memory stack must be 16-byte aligned.
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#endif
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/** Heavyweight interrupt handler
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/** Heavyweight interrupt handler
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 *
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 *
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 * This macro roughly follows steps from 1 to 19 described in
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 * This macro roughly follows steps from 1 to 19 described in
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 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
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 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
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    /* 3. switch to kernel memory stack */
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    /* 3. switch to kernel memory stack */
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	/* TODO: support interruptions from userspace */
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	/* TODO: support interruptions from userspace */
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	/* assume kernel stack */
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	/* assume kernel stack */
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    /* 4. save registers in bank 0 into memory stack */
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    /* 4. save registers in bank 0 into memory stack */
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	add r12 = -8, r12 ;;
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	add r31 = -8, r12 ;;
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	add r12 = -STACK_FRAME_SIZE, r12 ;;
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	st8 [r12] = r29, -8 ;;	/* save predicate registers */
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	st8 [r31] = r29, -8 ;;	/* save predicate registers */
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	st8 [r12] = r24, -8 ;;	/* save cr.iip */
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	st8 [r31] = r24, -8 ;;	/* save cr.iip */
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	st8 [r12] = r25, -8 ;;	/* save cr.ipsr */
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	st8 [r31] = r25, -8 ;;	/* save cr.ipsr */
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	st8 [r12] = r26, -8 ;;	/* save cr.iipa */
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	st8 [r31] = r26, -8 ;;	/* save cr.iipa */
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	st8 [r12] = r27, -8 ;;	/* save cr.isr */
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	st8 [r31] = r27, -8 ;;	/* save cr.isr */
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	st8 [r12] = r28, -8 ;;	/* save cr.ifa */
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	st8 [r31] = r28, -8 ;;	/* save cr.ifa */
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    /* 5. RSE switch from interrupted context */
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    /* 5. RSE switch from interrupted context */
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    	.auto
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    	.auto
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	mov r24 = ar.rsc
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	mov r24 = ar.rsc
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	mov r25 = ar.pfs
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	mov r25 = ar.pfs
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	cover
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	cover
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	mov r26 = cr.ifs
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	mov r26 = cr.ifs
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	st8 [r12] = r24, -8	/* save ar.rsc */
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	st8 [r31] = r24, -8	/* save ar.rsc */
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	st8 [r12] = r25, -8	/* save ar.pfs */
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	st8 [r31] = r25, -8	/* save ar.pfs */
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	st8 [r12] = r26, -8	/* save ar.ifs */
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	st8 [r31] = r26, -8	/* save ar.ifs */
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	and r30 = ~3, r24
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	and r30 = ~3, r24
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	mov ar.rsc = r30	/* place RSE in enforced lazy mode */
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	mov ar.rsc = r30	/* place RSE in enforced lazy mode */
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	mov r27 = ar.rnat
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	mov r27 = ar.rnat
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	/* assume kernel backing store */
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	/* assume kernel backing store */
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	mov ar.bspstore = r28
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	mov ar.bspstore = r28
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	mov r29 = ar.bsp
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	mov r29 = ar.bsp
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	st8 [r12] = r27, -8	/* save ar.rnat */
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	st8 [r31] = r27, -8	/* save ar.rnat */
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	st8 [r12] = r28, -8	/* save ar.bspstore */
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	st8 [r31] = r28, -8	/* save ar.bspstore */
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	st8 [r12] = r29		/* save ar.bsp */
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	st8 [r31] = r29		/* save ar.bsp */
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	mov ar.rsc = r24	/* restore RSE's setting */
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	mov ar.rsc = r24	/* restore RSE's setting */
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	.explicit
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	.explicit
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    /* the rest of the save-handler can be kept outside IVT */
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    /* the rest of the save-handler can be kept outside IVT */