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1 
#
 1 
#
2 
# Copyright (C) 2005 Jakub Vana
 2 
# Copyright (C) 2005 Jakub Vana
3 
# All rights reserved.
 3 
# All rights reserved.
4 
#
 4 
#
5 
# Redistribution and use in source and binary forms, with or without
 5 
# Redistribution and use in source and binary forms, with or without
6 
# modification, are permitted provided that the following conditions
 6 
# modification, are permitted provided that the following conditions
7 
# are met:
 7 
# are met:
8 
#
 8 
#
9 
# - Redistributions of source code must retain the above copyright
 9 
# - Redistributions of source code must retain the above copyright
10 
#   notice, this list of conditions and the following disclaimer.
 10 
#   notice, this list of conditions and the following disclaimer.
11 
# - Redistributions in binary form must reproduce the above copyright
 11 
# - Redistributions in binary form must reproduce the above copyright
12 
#   notice, this list of conditions and the following disclaimer in the
 12 
#   notice, this list of conditions and the following disclaimer in the
13 
#   documentation and/or other materials provided with the distribution.
 13 
#   documentation and/or other materials provided with the distribution.
14 
# - The name of the author may not be used to endorse or promote products
 14 
# - The name of the author may not be used to endorse or promote products
15 
#   derived from this software without specific prior written permission.
 15 
#   derived from this software without specific prior written permission.
16 
#
 16 
#
17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
 17 
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
 18 
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
 19 
# OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
 20 
# IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 21 
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
 22 
# NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
 23 
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 24 
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 25 
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 26 
# THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 
#
 27 
#
28 
 
 28 
 
29 
 
 29 
 
- 
 
 30 
/** Heavyweight interrupt handler
30 
/*
 31 
 *
31 
 * This macro roughly follows steps from 1 to 19 described in
 32 
 * This macro roughly follows steps from 1 to 19 described in
32 
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
 33 
 * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2.
33 
 *
 34 
 *
- 
 
 35 
 * HEAVYWEIGHT_HANDLER macro must cram into 16 bundles (48 instructions).
- 
 
 36 
 * This goal is achieved by using procedure calls after RSE becomes operational.
- 
 
 37 
 *
34 
 * Some steps are skipped (enabling and disabling interrupts).
 38 
 * Some steps are skipped (enabling and disabling interrupts).
35 
 * Some steps are not fully supported yet (e.g. interruptions
 39 
 * Some steps are not fully supported yet (e.g. interruptions
36 
 * from user space and floating-point context).
 40 
 * from userspace and floating-point context).
37 
 */
 41 
 */
38 
.macro HEAVYWEIGHT_HANDLER offs handler
 42 
.macro HEAVYWEIGHT_HANDLER offs handler
39 
    .org IVT + \offs
 43 
    .org IVT + \offs
40 
	SAVE_INTERRUPTED_CONTEXT		/* steps 1 - 9 */
 - 
 
41 
	br.call.sptk.many rp = \handler		/* steps 10 - 11 */
 - 
 
42 
	br restore_interrupted_context		/* steps 12 - 19 */
 - 
 
43 
.endm
 - 
 
44 
 
 44 
 
45 
.macro SAVE_INTERRUPTED_CONTEXT
 - 
 
46 
    /* 1. copy interrupt registers into bank 0 */
 45 
    /* 1. copy interrupt registers into bank 0 */
47 
	mov r24 = cr.iip
 46 
	mov r24 = cr.iip
48 
	mov r25 = cr.ipsr
 47 
	mov r25 = cr.ipsr
49 
	mov r26 = cr.iipa
 48 
	mov r26 = cr.iipa
50 
	mov r27 = cr.isr
 49 
	mov r27 = cr.isr
51 
	mov r28 = cr.ifa
 50 
	mov r28 = cr.ifa
52
51
53 
    /* 2. preserve predicate register into bank 0 */
 52 
    /* 2. preserve predicate register into bank 0 */
54 
	mov r29 = pr ;;
 53 
	mov r29 = pr ;;
55
54
56 
	/* 3. switch to kernel memory stack */
 55 
    /* 3. switch to kernel memory stack */
57 
	/* TODO: support interruptions from userspace */
 56 
	/* TODO: support interruptions from userspace */
58 
	/* assume kernel stack */
 57 
	/* assume kernel stack */
59
58
60 
    /* 4. allocate memory stack for registers saved in bank 0 */
 59 
    /* 4. allocate memory stack for registers saved in bank 0 */
61 
	st8 [r12] = r29, -8 ;;	/* save predicate registers */
 60 
	st8 [r12] = r29, -8 ;;	/* save predicate registers */
62 
	st8 [r12] = r28, -8 ;;	/* save cr.ifa */
 - 
 
63 
	st8 [r12] = r27, -8 ;;	/* save cr.isr */
 - 
 
64 
	st8 [r12] = r26, -8 ;;	/* save cr.iipa */
 - 
 
65 
	st8 [r12] = r25, -8 ;;	/* save cr.ipsr */
 - 
 
- 
 
 61 
 
66 
	st8 [r12] = r24, -8 ;;	/* save cr.iip */
 62 
	st8 [r12] = r24, -8 ;;	/* save cr.iip */
- 
 
 63 
	st8 [r12] = r25, -8 ;;	/* save cr.ipsr */
- 
 
 64 
	st8 [r12] = r26, -8 ;;	/* save cr.iipa */
- 
 
 65 
	st8 [r12] = r27, -8 ;;	/* save cr.isr */
- 
 
 66 
	st8 [r12] = r28, -8 ;;	/* save cr.ifa */
67
67 
 
68 
    /* 5. RSE switch */
 68 
    /* 5. RSE switch from interrupted context */
69 
    	.auto
 69 
    	.auto
70 
	mov r24 = ar.rsc
 70 
	mov r24 = ar.rsc
71 
	mov r25 = ar.pfs
 71 
	mov r25 = ar.pfs
72 
	cover
 72 
	cover
73 
	mov r26 = cr.ifs
 73 
	mov r26 = cr.ifs
74
74
75 
	st8 [r12] = r24, -8	/* save ar.rsc */
 75 
	st8 [r12] = r24, -8	/* save ar.rsc */
76 
	st8 [r12] = r25, -8	/* save ar.pfs */
 76 
	st8 [r12] = r25, -8	/* save ar.pfs */
77 
	st8 [r12] = r26, -8	/* save ar.ifs */
 77 
	st8 [r12] = r26, -8	/* save ar.ifs */
78
78
79 
	and r30 = ~3, r24
 79 
	and r30 = ~3, r24
80 
	mov ar.rsc = r30	/* place RSE in enforced lazy mode */
 80 
	mov ar.rsc = r30	/* place RSE in enforced lazy mode */
81
81
82 
	mov r27 = ar.rnat
 82 
	mov r27 = ar.rnat
83 
	mov r28 = ar.bspstore
 83 
	mov r28 = ar.bspstore
84
84
85 
	/* assume kernel backing store */
 85 
	/* assume kernel backing store */
86 
	mov ar.bspstore = r28
 86 
	mov ar.bspstore = r28
87
87
88 
	mov r29 = ar.bsp
 88 
	mov r29 = ar.bsp
89
89
90 
	st8 [r12] = r27, -8	/* save ar.rnat */
 90 
	st8 [r12] = r27, -8	/* save ar.rnat */
91 
	st8 [r12] = r28, -8	/* save ar.bspstore */
 91 
	st8 [r12] = r28, -8	/* save ar.bspstore */
92 
	st8 [r12] = r29, -8	/* save ar.bsp */
 92 
	st8 [r12] = r29, -8	/* save ar.bsp */
93
93
94 
	mov ar.rsc = r24	/* restore RSE's setting */
 94 
	mov ar.rsc = r24	/* restore RSE's setting */
95 
	.explicit
 95 
	.explicit
96
96
- 
 
 97 
    /* the rest of the save-handler can be kept outside IVT */
- 
 
 98 
 
- 
 
 99 
	movl r24 = \handler
- 
 
 100 
	mov r25 = b0
- 
 
 101 
	br.call.sptk.many rp = heavyweight_handler_inner
- 
 
 102 
0:	mov b0 = r25
- 
 
 103 
 
- 
 
 104 
	{ br heavyweight_handler_finalize }
- 
 
 105 
.endm
- 
 
 106 
 
- 
 
 107 
.global heavyweight_handler_inner
- 
 
 108 
heavyweight_handler_inner:
- 
 
 109 
	/*
- 
 
 110 
	 * From this point, the rest of the interrupted context
- 
 
 111 
	 * will be preserved in stacked registers and backing store.
- 
 
 112 
	 */
- 
 
 113 
	alloc loc0 = ar.pfs, 0, 46, 0, 0 ;;
- 
 
 114
- 
 
 115 
	/* copy handler address (r24 from bank 0 will be invisible soon) */
- 
 
 116 
	mov loc1 = r24
- 
 
 117 
 
97 
    /* 6. switch to bank 1 and reenable PSR.ic */
 118 
    /* 6. switch to bank 1 and reenable PSR.ic */
98 
	ssm 0x2000
 119 
	ssm 0x2000
99 
	bsw.1 ;;
 120 
	bsw.1 ;;
100 
	srlz.d
 121 
	srlz.d
101
122
102 
    /* 7. preserve branch and application registers */
 123 
    /* 7. preserve branch and application registers */
- 
 
 124 
    	mov loc2 = ar.unat
- 
 
 125 
	mov loc3 = ar.lc
- 
 
 126 
	mov loc4 = ar.ec
- 
 
 127 
	mov loc5 = ar.ccv
- 
 
 128 
	mov loc6 = ar.csd
- 
 
 129 
	mov loc7 = ar.ssd
- 
 
 130
- 
 
 131 
	mov loc8 = b0
- 
 
 132 
	mov loc9 = b1
- 
 
 133 
	mov loc10 = b2
- 
 
 134 
	mov loc11 = b3
- 
 
 135 
	mov loc12 = b4
- 
 
 136 
	mov loc13 = b5
- 
 
 137 
	mov loc14 = b6
- 
 
 138 
	mov loc15 = b7
103
139
104 
    /* 8. preserve general and floating-point registers */
 140 
    /* 8. preserve general and floating-point registers */
105 
	/* TODO: save floating-point context */
 141 
	/* TODO: save floating-point context */
- 
 
 142 
	mov loc16 = r1
- 
 
 143 
	mov loc17 = r2
- 
 
 144 
	mov loc18 = r3
- 
 
 145 
	mov loc19 = r4
- 
 
 146 
	mov loc20 = r5
- 
 
 147 
	mov loc21 = r6
- 
 
 148 
	mov loc22 = r7
- 
 
 149 
	mov loc23 = r8
- 
 
 150 
	mov loc24 = r9
- 
 
 151 
	mov loc25 = r10
- 
 
 152 
	mov loc26 = r11
- 
 
 153 
	/* skip r12 (stack pointer) */
- 
 
 154 
	mov loc27 = r13
- 
 
 155 
	mov loc28 = r14
- 
 
 156 
	mov loc29 = r15
- 
 
 157 
	mov loc30 = r16
- 
 
 158 
	mov loc31 = r17
- 
 
 159 
	mov loc32 = r18
- 
 
 160 
	mov loc33 = r19
- 
 
 161 
	mov loc34 = r20
- 
 
 162 
	mov loc35 = r21
- 
 
 163 
	mov loc36 = r22
- 
 
 164 
	mov loc37 = r23
- 
 
 165 
	mov loc38 = r24
- 
 
 166 
	mov loc39 = r25
- 
 
 167 
	mov loc40 = r26
- 
 
 168 
	mov loc41 = r27
- 
 
 169 
	mov loc42 = r28
- 
 
 170 
	mov loc43 = r29
- 
 
 171 
	mov loc44 = r30
- 
 
 172 
	mov loc45 = r31
106
173
107 
    /* 9. skipped (will not enable interrupts) */
 174 
    /* 9. skipped (will not enable interrupts) */
108 
.endm
 - 
 
109 
 
 175 
 
- 
 
 176 
    /* 10. call handler */
- 
 
 177 
    	mov b1 = loc1
110 
.macro RESTORE_INTERRUPTED_CONTEXT
 178 
	br.call.sptk.many b0 = b1
- 
 
 179 
 
111 
    /* 12. skipped (will not disable interrupts) */
 180 
    /* 11. return from handler */
- 
 
 181 
0:
112
182
- 
 
 183 
    /* 12. skipped (will not disable interrupts) */
- 
 
 184 
 
113 
    /* 13. restore general and floating-point registers */
 185 
    /* 13. restore general and floating-point registers */
114 
	/* TODO: restore floating-point context */
 186 
	/* TODO: restore floating-point context */
- 
 
 187 
	mov r1 = loc16
- 
 
 188 
	mov r2 = loc17
- 
 
 189 
	mov r3 = loc18
- 
 
 190 
	mov r4 = loc19
- 
 
 191 
	mov r5 = loc20
- 
 
 192 
	mov r6 = loc21
- 
 
 193 
	mov r7 = loc22
- 
 
 194 
	mov r8 = loc23
- 
 
 195 
	mov r9 = loc24
- 
 
 196 
	mov r10 = loc25
- 
 
 197 
	mov r11 = loc26
- 
 
 198 
	/* skip r12 (stack pointer) */
- 
 
 199 
	mov r13 = loc27
- 
 
 200 
	mov r14 = loc28
- 
 
 201 
	mov r15 = loc29
- 
 
 202 
	mov r16 = loc30
- 
 
 203 
	mov r17 = loc31
- 
 
 204 
	mov r18 = loc32
- 
 
 205 
	mov r19 = loc33
- 
 
 206 
	mov r20 = loc34
- 
 
 207 
	mov r21 = loc35
- 
 
 208 
	mov r22 = loc36
- 
 
 209 
	mov r23 = loc37
- 
 
 210 
	mov r24 = loc38
- 
 
 211 
	mov r25 = loc39
- 
 
 212 
	mov r26 = loc40
- 
 
 213 
	mov r27 = loc41
- 
 
 214 
	mov r28 = loc42
- 
 
 215 
	mov r29 = loc43
- 
 
 216 
	mov r30 = loc44
- 
 
 217 
	mov r31 = loc45
115
218
116 
    /* 14. restore branch and application registers */
 219 
    /* 14. restore branch and application registers */
- 
 
 220 
    	mov ar.unat = loc2
- 
 
 221 
	mov ar.lc = loc3
- 
 
 222 
	mov ar.ec = loc4
- 
 
 223 
	mov ar.ccv = loc5
- 
 
 224 
	mov ar.csd = loc6
- 
 
 225 
	mov ar.ssd = loc7
- 
 
 226
- 
 
 227 
	mov b0 = loc8
- 
 
 228 
	mov b1 = loc9
- 
 
 229 
	mov b2 = loc10
- 
 
 230 
	mov b3 = loc11
- 
 
 231 
	mov b4 = loc12
- 
 
 232 
	mov b5 = loc13
- 
 
 233 
	mov b6 = loc14
- 
 
 234 
	mov b7 = loc15
117
235
118 
    /* 15. disable PSR.ic and switch to bank 0 */
 236 
    /* 15. disable PSR.ic and switch to bank 0 */
119 
	rsm 0x2000
 237 
	rsm 0x2000
120 
	bsw.0 ;;
 238 
	bsw.0 ;;
121 
	srlz.d
 239 
	srlz.d
- 
 
 240 
 
- 
 
 241 
	mov ar.pfs = loc0
- 
 
 242 
	br.ret.sptk.many rp
122
243 
 
- 
 
 244 
.global heavyweight_handler_finalize
- 
 
 245 
heavyweight_handler_finalize:
123 
    /* 16. RSE switch */
 246 
    /* 16. RSE switch to interrupted context */
124
247
125 
    /* 17. restore interruption state from memory stack */
 248 
    /* 17. restore interruption state from memory stack */
126
249
127 
    /* 18. restore predicate registers from memory stack */
 250 
    /* 18. restore predicate registers from memory stack */
128
251
129 
    /* 19. return from interruption */
 252 
    /* 19. return from interruption */
130 
	rfi
 253 
	rfi
131 
.endm
 - 
 
132 
 
 254 
 
133 
.global restore_interrupted_context
 - 
 
134 
restore_interrupted_context:
 - 
 
135 
	RESTORE_INTERRUPTED_CONTEXT
 - 
 
136 
	/* not reached */
 - 
 
- 
 
 255 
 
- 
 
 256 
 
137 
 
 257 
 
138 
dump_gregs:
 258 
dump_gregs:
139 
mov r16 = REG_DUMP;;
 259 
mov r16 = REG_DUMP;;
140 
st8 [r16] = r0;;
 260 
st8 [r16] = r0;;
141 
add r16 = 8,r16 ;;
 261 
add r16 = 8,r16 ;;
142 
st8 [r16] = r1;;
 262 
st8 [r16] = r1;;
143 
add r16 = 8,r16 ;;
 263 
add r16 = 8,r16 ;;
144 
st8 [r16] = r2;;
 264 
st8 [r16] = r2;;
145 
add r16 = 8,r16 ;;
 265 
add r16 = 8,r16 ;;
146 
st8 [r16] = r3;;
 266 
st8 [r16] = r3;;
147 
add r16 = 8,r16 ;;
 267 
add r16 = 8,r16 ;;
148 
st8 [r16] = r4;;
 268 
st8 [r16] = r4;;
149 
add r16 = 8,r16 ;;
 269 
add r16 = 8,r16 ;;
150 
st8 [r16] = r5;;
 270 
st8 [r16] = r5;;
151 
add r16 = 8,r16 ;;
 271 
add r16 = 8,r16 ;;
152 
st8 [r16] = r6;;
 272 
st8 [r16] = r6;;
153 
add r16 = 8,r16 ;;
 273 
add r16 = 8,r16 ;;
154 
st8 [r16] = r7;;
 274 
st8 [r16] = r7;;
155 
add r16 = 8,r16 ;;
 275 
add r16 = 8,r16 ;;
156 
st8 [r16] = r8;;
 276 
st8 [r16] = r8;;
157 
add r16 = 8,r16 ;;
 277 
add r16 = 8,r16 ;;
158 
st8 [r16] = r9;;
 278 
st8 [r16] = r9;;
159 
add r16 = 8,r16 ;;
 279 
add r16 = 8,r16 ;;
160 
st8 [r16] = r10;;
 280 
st8 [r16] = r10;;
161 
add r16 = 8,r16 ;;
 281 
add r16 = 8,r16 ;;
162 
st8 [r16] = r11;;
 282 
st8 [r16] = r11;;
163 
add r16 = 8,r16 ;;
 283 
add r16 = 8,r16 ;;
164 
st8 [r16] = r12;;
 284 
st8 [r16] = r12;;
165 
add r16 = 8,r16 ;;
 285 
add r16 = 8,r16 ;;
166 
st8 [r16] = r13;;
 286 
st8 [r16] = r13;;
167 
add r16 = 8,r16 ;;
 287 
add r16 = 8,r16 ;;
168 
st8 [r16] = r14;;
 288 
st8 [r16] = r14;;
169 
add r16 = 8,r16 ;;
 289 
add r16 = 8,r16 ;;
170 
st8 [r16] = r15;;
 290 
st8 [r16] = r15;;
171 
add r16 = 8,r16 ;;
 291 
add r16 = 8,r16 ;;
172 
 
 292 
 
173 
bsw.1;;
 293 
bsw.1;;
174 
mov r15 = r16;;
 294 
mov r15 = r16;;
175 
bsw.0;;
 295 
bsw.0;;
176 
st8 [r16] = r15;;
 296 
st8 [r16] = r15;;
177 
add r16 = 8,r16 ;;
 297 
add r16 = 8,r16 ;;
178 
bsw.1;;
 298 
bsw.1;;
179 
mov r15 = r17;;
 299 
mov r15 = r17;;
180 
bsw.0;;
 300 
bsw.0;;
181 
st8 [r16] = r15;;
 301 
st8 [r16] = r15;;
182 
add r16 = 8,r16 ;;
 302 
add r16 = 8,r16 ;;
183 
bsw.1;;
 303 
bsw.1;;
184 
mov r15 = r18;;
 304 
mov r15 = r18;;
185 
bsw.0;;
 305 
bsw.0;;
186 
st8 [r16] = r15;;
 306 
st8 [r16] = r15;;
187 
add r16 = 8,r16 ;;
 307 
add r16 = 8,r16 ;;
188 
bsw.1;;
 308 
bsw.1;;
189 
mov r15 = r19;;
 309 
mov r15 = r19;;
190 
bsw.0;;
 310 
bsw.0;;
191 
st8 [r16] = r15;;
 311 
st8 [r16] = r15;;
192 
add r16 = 8,r16 ;;
 312 
add r16 = 8,r16 ;;
193 
bsw.1;;
 313 
bsw.1;;
194 
mov r15 = r20;;
 314 
mov r15 = r20;;
195 
bsw.0;;
 315 
bsw.0;;
196 
st8 [r16] = r15;;
 316 
st8 [r16] = r15;;
197 
add r16 = 8,r16 ;;
 317 
add r16 = 8,r16 ;;
198 
bsw.1;;
 318 
bsw.1;;
199 
mov r15 = r21;;
 319 
mov r15 = r21;;
200 
bsw.0;;
 320 
bsw.0;;
201 
st8 [r16] = r15;;
 321 
st8 [r16] = r15;;
202 
add r16 = 8,r16 ;;
 322 
add r16 = 8,r16 ;;
203 
bsw.1;;
 323 
bsw.1;;
204 
mov r15 = r22;;
 324 
mov r15 = r22;;
205 
bsw.0;;
 325 
bsw.0;;
206 
st8 [r16] = r15;;
 326 
st8 [r16] = r15;;
207 
add r16 = 8,r16 ;;
 327 
add r16 = 8,r16 ;;
208 
bsw.1;;
 328 
bsw.1;;
209 
mov r15 = r23;;
 329 
mov r15 = r23;;
210 
bsw.0;;
 330 
bsw.0;;
211 
st8 [r16] = r15;;
 331 
st8 [r16] = r15;;
212 
add r16 = 8,r16 ;;
 332 
add r16 = 8,r16 ;;
213 
bsw.1;;
 333 
bsw.1;;
214 
mov r15 = r24;;
 334 
mov r15 = r24;;
215 
bsw.0;;
 335 
bsw.0;;
216 
st8 [r16] = r15;;
 336 
st8 [r16] = r15;;
217 
add r16 = 8,r16 ;;
 337 
add r16 = 8,r16 ;;
218 
bsw.1;;
 338 
bsw.1;;
219 
mov r15 = r25;;
 339 
mov r15 = r25;;
220 
bsw.0;;
 340 
bsw.0;;
221 
st8 [r16] = r15;;
 341 
st8 [r16] = r15;;
222 
add r16 = 8,r16 ;;
 342 
add r16 = 8,r16 ;;
223 
bsw.1;;
 343 
bsw.1;;
224 
mov r15 = r26;;
 344 
mov r15 = r26;;
225 
bsw.0;;
 345 
bsw.0;;
226 
st8 [r16] = r15;;
 346 
st8 [r16] = r15;;
227 
add r16 = 8,r16 ;;
 347 
add r16 = 8,r16 ;;
228 
bsw.1;;
 348 
bsw.1;;
229 
mov r15 = r27;;
 349 
mov r15 = r27;;
230 
bsw.0;;
 350 
bsw.0;;
231 
st8 [r16] = r15;;
 351 
st8 [r16] = r15;;
232 
add r16 = 8,r16 ;;
 352 
add r16 = 8,r16 ;;
233 
bsw.1;;
 353 
bsw.1;;
234 
mov r15 = r28;;
 354 
mov r15 = r28;;
235 
bsw.0;;
 355 
bsw.0;;
236 
st8 [r16] = r15;;
 356 
st8 [r16] = r15;;
237 
add r16 = 8,r16 ;;
 357 
add r16 = 8,r16 ;;
238 
bsw.1;;
 358 
bsw.1;;
239 
mov r15 = r29;;
 359 
mov r15 = r29;;
240 
bsw.0;;
 360 
bsw.0;;
241 
st8 [r16] = r15;;
 361 
st8 [r16] = r15;;
242 
add r16 = 8,r16 ;;
 362 
add r16 = 8,r16 ;;
243 
bsw.1;;
 363 
bsw.1;;
244 
mov r15 = r30;;
 364 
mov r15 = r30;;
245 
bsw.0;;
 365 
bsw.0;;
246 
st8 [r16] = r15;;
 366 
st8 [r16] = r15;;
247 
add r16 = 8,r16 ;;
 367 
add r16 = 8,r16 ;;
248 
bsw.1;;
 368 
bsw.1;;
249 
mov r15 = r31;;
 369 
mov r15 = r31;;
250 
bsw.0;;
 370 
bsw.0;;
251 
st8 [r16] = r15;;
 371 
st8 [r16] = r15;;
252 
add r16 = 8,r16 ;;
 372 
add r16 = 8,r16 ;;
253 
 
 373 
 
254 
 
 374 
 
255 
st8 [r16] = r32;;
 375 
st8 [r16] = r32;;
256 
add r16 = 8,r16 ;;
 376 
add r16 = 8,r16 ;;
257 
st8 [r16] = r33;;
 377 
st8 [r16] = r33;;
258 
add r16 = 8,r16 ;;
 378 
add r16 = 8,r16 ;;
259 
st8 [r16] = r34;;
 379 
st8 [r16] = r34;;
260 
add r16 = 8,r16 ;;
 380 
add r16 = 8,r16 ;;
261 
st8 [r16] = r35;;
 381 
st8 [r16] = r35;;
262 
add r16 = 8,r16 ;;
 382 
add r16 = 8,r16 ;;
263 
st8 [r16] = r36;;
 383 
st8 [r16] = r36;;
264 
add r16 = 8,r16 ;;
 384 
add r16 = 8,r16 ;;
265 
st8 [r16] = r37;;
 385 
st8 [r16] = r37;;
266 
add r16 = 8,r16 ;;
 386 
add r16 = 8,r16 ;;
267 
st8 [r16] = r38;;
 387 
st8 [r16] = r38;;
268 
add r16 = 8,r16 ;;
 388 
add r16 = 8,r16 ;;
269 
st8 [r16] = r39;;
 389 
st8 [r16] = r39;;
270 
add r16 = 8,r16 ;;
 390 
add r16 = 8,r16 ;;
271 
st8 [r16] = r40;;
 391 
st8 [r16] = r40;;
272 
add r16 = 8,r16 ;;
 392 
add r16 = 8,r16 ;;
273 
st8 [r16] = r41;;
 393 
st8 [r16] = r41;;
274 
add r16 = 8,r16 ;;
 394 
add r16 = 8,r16 ;;
275 
st8 [r16] = r42;;
 395 
st8 [r16] = r42;;
276 
add r16 = 8,r16 ;;
 396 
add r16 = 8,r16 ;;
277 
st8 [r16] = r43;;
 397 
st8 [r16] = r43;;
278 
add r16 = 8,r16 ;;
 398 
add r16 = 8,r16 ;;
279 
st8 [r16] = r44;;
 399 
st8 [r16] = r44;;
280 
add r16 = 8,r16 ;;
 400 
add r16 = 8,r16 ;;
281 
st8 [r16] = r45;;
 401 
st8 [r16] = r45;;
282 
add r16 = 8,r16 ;;
 402 
add r16 = 8,r16 ;;
283 
st8 [r16] = r46;;
 403 
st8 [r16] = r46;;
284 
add r16 = 8,r16 ;;
 404 
add r16 = 8,r16 ;;
285 
st8 [r16] = r47;;
 405 
st8 [r16] = r47;;
286 
add r16 = 8,r16 ;;
 406 
add r16 = 8,r16 ;;
287 
st8 [r16] = r48;;
 407 
st8 [r16] = r48;;
288 
add r16 = 8,r16 ;;
 408 
add r16 = 8,r16 ;;
289 
st8 [r16] = r49;;
 409 
st8 [r16] = r49;;
290 
add r16 = 8,r16 ;;
 410 
add r16 = 8,r16 ;;
291 
st8 [r16] = r50;;
 411 
st8 [r16] = r50;;
292 
add r16 = 8,r16 ;;
 412 
add r16 = 8,r16 ;;
293 
st8 [r16] = r51;;
 413 
st8 [r16] = r51;;
294 
add r16 = 8,r16 ;;
 414 
add r16 = 8,r16 ;;
295 
st8 [r16] = r52;;
 415 
st8 [r16] = r52;;
296 
add r16 = 8,r16 ;;
 416 
add r16 = 8,r16 ;;
297 
st8 [r16] = r53;;
 417 
st8 [r16] = r53;;
298 
add r16 = 8,r16 ;;
 418 
add r16 = 8,r16 ;;
299 
st8 [r16] = r54;;
 419 
st8 [r16] = r54;;
300 
add r16 = 8,r16 ;;
 420 
add r16 = 8,r16 ;;
301 
st8 [r16] = r55;;
 421 
st8 [r16] = r55;;
302 
add r16 = 8,r16 ;;
 422 
add r16 = 8,r16 ;;
303 
st8 [r16] = r56;;
 423 
st8 [r16] = r56;;
304 
add r16 = 8,r16 ;;
 424 
add r16 = 8,r16 ;;
305 
st8 [r16] = r57;;
 425 
st8 [r16] = r57;;
306 
add r16 = 8,r16 ;;
 426 
add r16 = 8,r16 ;;
307 
st8 [r16] = r58;;
 427 
st8 [r16] = r58;;
308 
add r16 = 8,r16 ;;
 428 
add r16 = 8,r16 ;;
309 
st8 [r16] = r59;;
 429 
st8 [r16] = r59;;
310 
add r16 = 8,r16 ;;
 430 
add r16 = 8,r16 ;;
311 
st8 [r16] = r60;;
 431 
st8 [r16] = r60;;
312 
add r16 = 8,r16 ;;
 432 
add r16 = 8,r16 ;;
313 
st8 [r16] = r61;;
 433 
st8 [r16] = r61;;
314 
add r16 = 8,r16 ;;
 434 
add r16 = 8,r16 ;;
315 
st8 [r16] = r62;;
 435 
st8 [r16] = r62;;
316 
add r16 = 8,r16 ;;
 436 
add r16 = 8,r16 ;;
317 
st8 [r16] = r63;;
 437 
st8 [r16] = r63;;
318 
add r16 = 8,r16 ;;
 438 
add r16 = 8,r16 ;;
319 
 
 439 
 
320 
 
 440 
 
321 
 
 441 
 
322 
st8 [r16] = r64;;
 442 
st8 [r16] = r64;;
323 
add r16 = 8,r16 ;;
 443 
add r16 = 8,r16 ;;
324 
st8 [r16] = r65;;
 444 
st8 [r16] = r65;;
325 
add r16 = 8,r16 ;;
 445 
add r16 = 8,r16 ;;
326 
st8 [r16] = r66;;
 446 
st8 [r16] = r66;;
327 
add r16 = 8,r16 ;;
 447 
add r16 = 8,r16 ;;
328 
st8 [r16] = r67;;
 448 
st8 [r16] = r67;;
329 
add r16 = 8,r16 ;;
 449 
add r16 = 8,r16 ;;
330 
st8 [r16] = r68;;
 450 
st8 [r16] = r68;;
331 
add r16 = 8,r16 ;;
 451 
add r16 = 8,r16 ;;
332 
st8 [r16] = r69;;
 452 
st8 [r16] = r69;;
333 
add r16 = 8,r16 ;;
 453 
add r16 = 8,r16 ;;
334 
st8 [r16] = r70;;
 454 
st8 [r16] = r70;;
335 
add r16 = 8,r16 ;;
 455 
add r16 = 8,r16 ;;
336 
st8 [r16] = r71;;
 456 
st8 [r16] = r71;;
337 
add r16 = 8,r16 ;;
 457 
add r16 = 8,r16 ;;
338 
st8 [r16] = r72;;
 458 
st8 [r16] = r72;;
339 
add r16 = 8,r16 ;;
 459 
add r16 = 8,r16 ;;
340 
st8 [r16] = r73;;
 460 
st8 [r16] = r73;;
341 
add r16 = 8,r16 ;;
 461 
add r16 = 8,r16 ;;
342 
st8 [r16] = r74;;
 462 
st8 [r16] = r74;;
343 
add r16 = 8,r16 ;;
 463 
add r16 = 8,r16 ;;
344 
st8 [r16] = r75;;
 464 
st8 [r16] = r75;;
345 
add r16 = 8,r16 ;;
 465 
add r16 = 8,r16 ;;
346 
st8 [r16] = r76;;
 466 
st8 [r16] = r76;;
347 
add r16 = 8,r16 ;;
 467 
add r16 = 8,r16 ;;
348 
st8 [r16] = r77;;
 468 
st8 [r16] = r77;;
349 
add r16 = 8,r16 ;;
 469 
add r16 = 8,r16 ;;
350 
st8 [r16] = r78;;
 470 
st8 [r16] = r78;;
351 
add r16 = 8,r16 ;;
 471 
add r16 = 8,r16 ;;
352 
st8 [r16] = r79;;
 472 
st8 [r16] = r79;;
353 
add r16 = 8,r16 ;;
 473 
add r16 = 8,r16 ;;
354 
st8 [r16] = r80;;
 474 
st8 [r16] = r80;;
355 
add r16 = 8,r16 ;;
 475 
add r16 = 8,r16 ;;
356 
st8 [r16] = r81;;
 476 
st8 [r16] = r81;;
357 
add r16 = 8,r16 ;;
 477 
add r16 = 8,r16 ;;
358 
st8 [r16] = r82;;
 478 
st8 [r16] = r82;;
359 
add r16 = 8,r16 ;;
 479 
add r16 = 8,r16 ;;
360 
st8 [r16] = r83;;
 480 
st8 [r16] = r83;;
361 
add r16 = 8,r16 ;;
 481 
add r16 = 8,r16 ;;
362 
st8 [r16] = r84;;
 482 
st8 [r16] = r84;;
363 
add r16 = 8,r16 ;;
 483 
add r16 = 8,r16 ;;
364 
st8 [r16] = r85;;
 484 
st8 [r16] = r85;;
365 
add r16 = 8,r16 ;;
 485 
add r16 = 8,r16 ;;
366 
st8 [r16] = r86;;
 486 
st8 [r16] = r86;;
367 
add r16 = 8,r16 ;;
 487 
add r16 = 8,r16 ;;
368 
st8 [r16] = r87;;
 488 
st8 [r16] = r87;;
369 
add r16 = 8,r16 ;;
 489 
add r16 = 8,r16 ;;
370 
st8 [r16] = r88;;
 490 
st8 [r16] = r88;;
371 
add r16 = 8,r16 ;;
 491 
add r16 = 8,r16 ;;
372 
st8 [r16] = r89;;
 492 
st8 [r16] = r89;;
373 
add r16 = 8,r16 ;;
 493 
add r16 = 8,r16 ;;
374 
st8 [r16] = r90;;
 494 
st8 [r16] = r90;;
375 
add r16 = 8,r16 ;;
 495 
add r16 = 8,r16 ;;
376 
st8 [r16] = r91;;
 496 
st8 [r16] = r91;;
377 
add r16 = 8,r16 ;;
 497 
add r16 = 8,r16 ;;
378 
st8 [r16] = r92;;
 498 
st8 [r16] = r92;;
379 
add r16 = 8,r16 ;;
 499 
add r16 = 8,r16 ;;
380 
st8 [r16] = r93;;
 500 
st8 [r16] = r93;;
381 
add r16 = 8,r16 ;;
 501 
add r16 = 8,r16 ;;
382 
st8 [r16] = r94;;
 502 
st8 [r16] = r94;;
383 
add r16 = 8,r16 ;;
 503 
add r16 = 8,r16 ;;
384 
st8 [r16] = r95;;
 504 
st8 [r16] = r95;;
385 
add r16 = 8,r16 ;;
 505 
add r16 = 8,r16 ;;
386 
 
 506 
 
387 
 
 507 
 
388 
 
 508 
 
389 
st8 [r16] = r96;;
 509 
st8 [r16] = r96;;
390 
add r16 = 8,r16 ;;
 510 
add r16 = 8,r16 ;;
391 
st8 [r16] = r97;;
 511 
st8 [r16] = r97;;
392 
add r16 = 8,r16 ;;
 512 
add r16 = 8,r16 ;;
393 
st8 [r16] = r98;;
 513 
st8 [r16] = r98;;
394 
add r16 = 8,r16 ;;
 514 
add r16 = 8,r16 ;;
395 
st8 [r16] = r99;;
 515 
st8 [r16] = r99;;
396 
add r16 = 8,r16 ;;
 516 
add r16 = 8,r16 ;;
397 
st8 [r16] = r100;;
 517 
st8 [r16] = r100;;
398 
add r16 = 8,r16 ;;
 518 
add r16 = 8,r16 ;;
399 
st8 [r16] = r101;;
 519 
st8 [r16] = r101;;
400 
add r16 = 8,r16 ;;
 520 
add r16 = 8,r16 ;;
401 
st8 [r16] = r102;;
 521 
st8 [r16] = r102;;
402 
add r16 = 8,r16 ;;
 522 
add r16 = 8,r16 ;;
403 
st8 [r16] = r103;;
 523 
st8 [r16] = r103;;
404 
add r16 = 8,r16 ;;
 524 
add r16 = 8,r16 ;;
405 
st8 [r16] = r104;;
 525 
st8 [r16] = r104;;
406 
add r16 = 8,r16 ;;
 526 
add r16 = 8,r16 ;;
407 
st8 [r16] = r105;;
 527 
st8 [r16] = r105;;
408 
add r16 = 8,r16 ;;
 528 
add r16 = 8,r16 ;;
409 
st8 [r16] = r106;;
 529 
st8 [r16] = r106;;
410 
add r16 = 8,r16 ;;
 530 
add r16 = 8,r16 ;;
411 
st8 [r16] = r107;;
 531 
st8 [r16] = r107;;
412 
add r16 = 8,r16 ;;
 532 
add r16 = 8,r16 ;;
413 
st8 [r16] = r108;;
 533 
st8 [r16] = r108;;
414 
add r16 = 8,r16 ;;
 534 
add r16 = 8,r16 ;;
415 
st8 [r16] = r109;;
 535 
st8 [r16] = r109;;
416 
add r16 = 8,r16 ;;
 536 
add r16 = 8,r16 ;;
417 
st8 [r16] = r110;;
 537 
st8 [r16] = r110;;
418 
add r16 = 8,r16 ;;
 538 
add r16 = 8,r16 ;;
419 
st8 [r16] = r111;;
 539 
st8 [r16] = r111;;
420 
add r16 = 8,r16 ;;
 540 
add r16 = 8,r16 ;;
421 
st8 [r16] = r112;;
 541 
st8 [r16] = r112;;
422 
add r16 = 8,r16 ;;
 542 
add r16 = 8,r16 ;;
423 
st8 [r16] = r113;;
 543 
st8 [r16] = r113;;
424 
add r16 = 8,r16 ;;
 544 
add r16 = 8,r16 ;;
425 
st8 [r16] = r114;;
 545 
st8 [r16] = r114;;
426 
add r16 = 8,r16 ;;
 546 
add r16 = 8,r16 ;;
427 
st8 [r16] = r115;;
 547 
st8 [r16] = r115;;
428 
add r16 = 8,r16 ;;
 548 
add r16 = 8,r16 ;;
429 
st8 [r16] = r116;;
 549 
st8 [r16] = r116;;
430 
add r16 = 8,r16 ;;
 550 
add r16 = 8,r16 ;;
431 
st8 [r16] = r117;;
 551 
st8 [r16] = r117;;
432 
add r16 = 8,r16 ;;
 552 
add r16 = 8,r16 ;;
433 
st8 [r16] = r118;;
 553 
st8 [r16] = r118;;
434 
add r16 = 8,r16 ;;
 554 
add r16 = 8,r16 ;;
435 
st8 [r16] = r119;;
 555 
st8 [r16] = r119;;
436 
add r16 = 8,r16 ;;
 556 
add r16 = 8,r16 ;;
437 
st8 [r16] = r120;;
 557 
st8 [r16] = r120;;
438 
add r16 = 8,r16 ;;
 558 
add r16 = 8,r16 ;;
439 
st8 [r16] = r121;;
 559 
st8 [r16] = r121;;
440 
add r16 = 8,r16 ;;
 560 
add r16 = 8,r16 ;;
441 
st8 [r16] = r122;;
 561 
st8 [r16] = r122;;
442 
add r16 = 8,r16 ;;
 562 
add r16 = 8,r16 ;;
443 
st8 [r16] = r123;;
 563 
st8 [r16] = r123;;
444 
add r16 = 8,r16 ;;
 564 
add r16 = 8,r16 ;;
445 
st8 [r16] = r124;;
 565 
st8 [r16] = r124;;
446 
add r16 = 8,r16 ;;
 566 
add r16 = 8,r16 ;;
447 
st8 [r16] = r125;;
 567 
st8 [r16] = r125;;
448 
add r16 = 8,r16 ;;
 568 
add r16 = 8,r16 ;;
449 
st8 [r16] = r126;;
 569 
st8 [r16] = r126;;
450 
add r16 = 8,r16 ;;
 570 
add r16 = 8,r16 ;;
451 
st8 [r16] = r127;;
 571 
st8 [r16] = r127;;
452 
add r16 = 8,r16 ;;
 572 
add r16 = 8,r16 ;;
453 
 
 573 
 
454 
 
 574 
 
455 
 
 575 
 
456 
br.ret.sptk.many b0;;
 576 
br.ret.sptk.many b0;;
457 
 
 577 
 
458 
 
 578 
 
459 
 
 579 
 
460 
 
 580 
 
461 
 
 581 
 
462 
.macro Handler o h
 582 
.macro Handler o h
463 
.org IVT + \o
 583 
.org IVT + \o
464 
br \h;;
 584 
br \h;;
465 
.endm
 585 
.endm
466 
 
 586 
 
467 
.macro Handler2 o
587 
.macro Handler2 o
468 
.org IVT + \o
 588 
.org IVT + \o
469 
br.call.sptk.many b0 = dump_gregs;;
 589 
br.call.sptk.many b0 = dump_gregs;;
470 
mov r16 = \o ;;
 590 
mov r16 = \o ;;
471 
bsw.1;;
 591 
bsw.1;;
472 
br universal_handler;;
 592 
br universal_handler;;
473 
.endm
 593 
.endm
474 
 
 594 
 
475 
 
 595 
 
476 
 
 596 
 
477 
.global IVT
 597 
.global IVT
478 
.align 32768
 598 
.align 32768
479 
IVT:
 599 
IVT:
480 
 
 600 
 
481 
 
 601 
 
482 
Handler2 0x0000
 602 
Handler2 0x0000
483 
Handler2 0x0400
 603 
Handler2 0x0400
484 
Handler2 0x0800
 604 
Handler2 0x0800
485 
Handler2 0x0c00
 605 
Handler2 0x0c00
486 
Handler2 0x1000
 606 
Handler2 0x1000
487 
Handler2 0x1400
 607 
Handler2 0x1400
488 
Handler2 0x1800
 608 
Handler2 0x1800
489 
Handler2 0x1c00
 609 
Handler2 0x1c00
490 
Handler2 0x2000
 610 
Handler2 0x2000
491 
Handler2 0x2400
 611 
Handler2 0x2400
492 
Handler2 0x2800
 612 
Handler2 0x2800
493 
Handler 0x2c00 break_instruction
 613 
Handler 0x2c00 break_instruction
494 
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
 614 
HEAVYWEIGHT_HANDLER 0x3000 external_interrupt	/* For external interrupt, heavyweight handler is used. */
495 
Handler2 0x3400
 615 
Handler2 0x3400
496 
Handler2 0x3800
 616 
Handler2 0x3800
497 
Handler2 0x3c00
 617 
Handler2 0x3c00
498 
Handler2 0x4000
 618 
Handler2 0x4000
499 
Handler2 0x4400
 619 
Handler2 0x4400
500 
Handler2 0x4800
 620 
Handler2 0x4800
501 
Handler2 0x4c00
 621 
Handler2 0x4c00
502 
 
 622 
 
503 
Handler2 0x5000
 623 
Handler2 0x5000
504 
Handler2 0x5100
 624 
Handler2 0x5100
505 
Handler2 0x5200
 625 
Handler2 0x5200
506 
Handler2 0x5300
 626 
Handler2 0x5300
507 
#Handler 0x5400 general_exception
 627 
#Handler 0x5400 general_exception
508 
Handler2 0x5400
 628 
Handler2 0x5400
509 
Handler2 0x5500
 629 
Handler2 0x5500
510 
Handler2 0x5600
 630 
Handler2 0x5600
511 
Handler2 0x5700
 631 
Handler2 0x5700
512 
Handler2 0x5800
 632 
Handler2 0x5800
513 
Handler2 0x5900
 633 
Handler2 0x5900
514 
Handler2 0x5a00
 634 
Handler2 0x5a00
515 
Handler2 0x5b00
 635 
Handler2 0x5b00
516 
Handler2 0x5c00
 636 
Handler2 0x5c00
517 
Handler2 0x5d00
 637 
Handler2 0x5d00
518 
Handler2 0x5e00
 638 
Handler2 0x5e00
519 
Handler2 0x5f00
 639 
Handler2 0x5f00
520 
 
 640 
 
521 
Handler2 0x6000
 641 
Handler2 0x6000
522 
Handler2 0x6100
 642 
Handler2 0x6100
523 
Handler2 0x6200
 643 
Handler2 0x6200
524 
Handler2 0x6300
 644 
Handler2 0x6300
525 
Handler2 0x6400
 645 
Handler2 0x6400
526 
Handler2 0x6500
 646 
Handler2 0x6500
527 
Handler2 0x6600
 647 
Handler2 0x6600
528 
Handler2 0x6700
 648 
Handler2 0x6700
529 
Handler2 0x6800
 649 
Handler2 0x6800
530 
Handler2 0x6900
 650 
Handler2 0x6900
531 
Handler2 0x6a00
 651 
Handler2 0x6a00
532 
Handler2 0x6b00
 652 
Handler2 0x6b00
533 
Handler2 0x6c00
 653 
Handler2 0x6c00
534 
Handler2 0x6d00
 654 
Handler2 0x6d00
535 
Handler2 0x6e00
 655 
Handler2 0x6e00
536 
Handler2 0x6f00
 656 
Handler2 0x6f00
537 
 
 657 
 
538 
Handler2 0x7000
 658 
Handler2 0x7000
539 
Handler2 0x7100
 659 
Handler2 0x7100
540 
Handler2 0x7200
 660 
Handler2 0x7200
541 
Handler2 0x7300
 661 
Handler2 0x7300
542 
Handler2 0x7400
 662 
Handler2 0x7400
543 
Handler2 0x7500
 663 
Handler2 0x7500
544 
Handler2 0x7600
 664 
Handler2 0x7600
545 
Handler2 0x7700
 665 
Handler2 0x7700
546 
Handler2 0x7800
 666 
Handler2 0x7800
547 
Handler2 0x7900
 667 
Handler2 0x7900
548 
Handler2 0x7a00
 668 
Handler2 0x7a00
549 
Handler2 0x7b00
 669 
Handler2 0x7b00
550 
Handler2 0x7c00
 670 
Handler2 0x7c00
551 
Handler2 0x7d00
 671 
Handler2 0x7d00
552 
Handler2 0x7e00
 672 
Handler2 0x7e00
553 
Handler2 0x7f00
 673 
Handler2 0x7f00
554 
 
 674 
 
555 
 
 675 
 
556 
 
 676 
 
557 
 
 677 
 
558 
 
 678 
 
559 
 
 679 
 
560 
 
 680 
 
561 
 
 681 
 
562 
.align 32768
 682 
.align 32768
563 
.global REG_DUMP
 683 
.global REG_DUMP
564 
 
 684 
 
565 
REG_DUMP:
 685 
REG_DUMP:
566 
.space 128*8
 686 
.space 128*8
567 
 
 687 
 
568 
 
 688