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| 25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
25 | # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
| 26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
26 | # THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 27 | # |
27 | # |
| 28 | 28 | ||
| 29 | 29 | ||
| - | 30 | /* |
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| - | 31 | * This macro roughly follows steps from 1 to 19 described in |
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| - | 32 | * Intel Itanium Architecture Software Developer's Manual, Chapter 3.4.2. |
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| - | 33 | * |
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| - | 34 | * Some steps are skipped (enabling and disabling interrupts). |
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| - | 35 | * Some steps are not fully supported yet (e.g. interruptions |
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| - | 36 | * from user space and floating-point context). |
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| - | 37 | */ |
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| - | 38 | .macro HEAVYWEIGHT_HANDLER offs handler |
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| - | 39 | .org IVT + \offs |
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| - | 40 | SAVE_INTERRUPTED_CONTEXT /* steps 1 - 9 */ |
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| - | 41 | br.call.sptk.many rp = \handler /* steps 10 - 11 */ |
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| - | 42 | br restore_interrupted_context /* steps 12 - 19 */ |
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| - | 43 | .endm |
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| - | 44 | ||
| - | 45 | .macro SAVE_INTERRUPTED_CONTEXT |
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| - | 46 | /* 1. copy interrupt registers into bank 0 */ |
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| - | 47 | mov r24 = cr.iip |
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| - | 48 | mov r25 = cr.ipsr |
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| - | 49 | mov r26 = cr.iipa |
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| - | 50 | mov r27 = cr.isr |
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| - | 51 | mov r28 = cr.ifa |
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| - | 52 | ||
| - | 53 | /* 2. preserve predicate register into bank 0 */ |
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| - | 54 | mov r29 = pr ;; |
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| - | 55 | ||
| - | 56 | /* 3. switch to kernel memory stack */ |
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| - | 57 | /* TODO: support interruptions from userspace */ |
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| - | 58 | /* assume kernel stack */ |
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| - | 59 | ||
| - | 60 | /* 4. allocate memory stack for registers saved in bank 0 */ |
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| - | 61 | st8 [r12] = r29, -8 ;; /* save predicate registers */ |
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| - | 62 | st8 [r12] = r28, -8 ;; /* save cr.ifa */ |
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| - | 63 | st8 [r12] = r27, -8 ;; /* save cr.isr */ |
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| - | 64 | st8 [r12] = r26, -8 ;; /* save cr.iipa */ |
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| - | 65 | st8 [r12] = r25, -8 ;; /* save cr.ipsr */ |
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| - | 66 | st8 [r12] = r24, -8 ;; /* save cr.iip */ |
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| - | 67 | ||
| - | 68 | /* 5. RSE switch */ |
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| - | 69 | .auto |
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| - | 70 | mov r24 = ar.rsc |
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| - | 71 | mov r25 = ar.pfs |
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| - | 72 | cover |
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| - | 73 | mov r26 = cr.ifs |
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| - | 74 | ||
| - | 75 | st8 [r12] = r24, -8 /* save ar.rsc */ |
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| - | 76 | st8 [r12] = r25, -8 /* save ar.pfs */ |
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| - | 77 | st8 [r12] = r26, -8 /* save ar.ifs */ |
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| - | 78 | ||
| - | 79 | and r30 = ~3, r24 |
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| - | 80 | mov ar.rsc = r30 /* place RSE in enforced lazy mode */ |
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| - | 81 | ||
| - | 82 | mov r27 = ar.rnat |
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| - | 83 | mov r28 = ar.bspstore |
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| - | 84 | ||
| - | 85 | /* assume kernel backing store */ |
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| - | 86 | mov ar.bspstore = r28 |
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| - | 87 | ||
| - | 88 | mov r29 = ar.bsp |
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| - | 89 | ||
| - | 90 | st8 [r12] = r27, -8 /* save ar.rnat */ |
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| - | 91 | st8 [r12] = r28, -8 /* save ar.bspstore */ |
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| - | 92 | st8 [r12] = r29, -8 /* save ar.bsp */ |
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| - | 93 | ||
| - | 94 | mov ar.rsc = r24 /* restore RSE's setting */ |
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| - | 95 | .explicit |
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| - | 96 | ||
| - | 97 | /* 6. switch to bank 1 and reenable PSR.ic */ |
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| - | 98 | ssm 0x2000 |
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| - | 99 | bsw.1 ;; |
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| - | 100 | srlz.d |
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| - | 101 | ||
| - | 102 | /* 7. preserve branch and application registers */ |
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| - | 103 | ||
| - | 104 | /* 8. preserve general and floating-point registers */ |
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| - | 105 | /* TODO: save floating-point context */ |
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| - | 106 | ||
| - | 107 | /* 9. skipped (will not enable interrupts) */ |
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| - | 108 | .endm |
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| - | 109 | ||
| - | 110 | .macro RESTORE_INTERRUPTED_CONTEXT |
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| - | 111 | /* 12. skipped (will not disable interrupts) */ |
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| - | 112 | ||
| - | 113 | /* 13. restore general and floating-point registers */ |
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| - | 114 | /* TODO: restore floating-point context */ |
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| - | 115 | ||
| - | 116 | /* 14. restore branch and application registers */ |
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| - | 117 | ||
| - | 118 | /* 15. disable PSR.ic and switch to bank 0 */ |
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| - | 119 | rsm 0x2000 |
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| - | 120 | bsw.0 ;; |
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| - | 121 | srlz.d |
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| - | 122 | ||
| - | 123 | /* 16. RSE switch */ |
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| - | 124 | ||
| - | 125 | /* 17. restore interruption state from memory stack */ |
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| - | 126 | ||
| - | 127 | /* 18. restore predicate registers from memory stack */ |
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| - | 128 | ||
| - | 129 | /* 19. return from interruption */ |
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| - | 130 | rfi |
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| - | 131 | .endm |
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| 30 | 132 | ||
| - | 133 | .global restore_interrupted_context |
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| - | 134 | restore_interrupted_context: |
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| - | 135 | RESTORE_INTERRUPTED_CONTEXT |
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| - | 136 | /* not reached */ |
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| 31 | 137 | ||
| 32 | dump_gregs: |
138 | dump_gregs: |
| 33 | mov r16 = REG_DUMP;; |
139 | mov r16 = REG_DUMP;; |
| 34 | st8 [r16] = r0;; |
140 | st8 [r16] = r0;; |
| 35 | add r16 = 8,r16 ;; |
141 | add r16 = 8,r16 ;; |
| Line 383... | Line 489... | ||
| 383 | Handler2 0x1c00 |
489 | Handler2 0x1c00 |
| 384 | Handler2 0x2000 |
490 | Handler2 0x2000 |
| 385 | Handler2 0x2400 |
491 | Handler2 0x2400 |
| 386 | Handler2 0x2800 |
492 | Handler2 0x2800 |
| 387 | Handler 0x2c00 break_instruction |
493 | Handler 0x2c00 break_instruction |
| 388 | Handler 0x3000 external_interrupt |
494 | HEAVYWEIGHT_HANDLER 0x3000 external_interrupt /* For external interrupt, heavyweight handler is used. */ |
| 389 | Handler2 0x3400 |
495 | Handler2 0x3400 |
| 390 | Handler2 0x3800 |
496 | Handler2 0x3800 |
| 391 | Handler2 0x3c00 |
497 | Handler2 0x3c00 |
| 392 | Handler2 0x4000 |
498 | Handler2 0x4000 |
| 393 | Handler2 0x4400 |
499 | Handler2 0x4400 |