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#ifndef __ia64_ASM_H__
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#ifndef __ia64_ASM_H__
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#define __ia64_ASM_H__
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#define __ia64_ASM_H__
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#include <arch/types.h>
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#include <arch/types.h>
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#include <config.h>
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#include <config.h>
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#include <arch/register.h>
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/** Return base address of current stack
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/** Return base address of current stack
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 *
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 *
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 * Return the base address of the current stack.
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 * Return the base address of the current stack.
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 * The stack is assumed to be STACK_SIZE long.
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 * The stack is assumed to be STACK_SIZE long.
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    __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    __asm__ volatile ("and %0 = %1, r12" : "=r" (v) : "r" (~(STACK_SIZE-1)));
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    return v;
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    return v;
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}
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}
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/** Read IVR (External Interrupt Vector Register)
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/** Read IVR (External Interrupt Vector Register).
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 *
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 *
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 * @return Highest priority, pending, unmasked external interrupt vector.
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 * @return Highest priority, pending, unmasked external interrupt vector.
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 */
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 */
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static inline __u8 read_ivr(void)
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static inline __u64 ivr_read(void)
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{
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{
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    __u64 v;
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    __u64 v;
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    __asm__ volatile ("mov %0 = cr65\n" : "=r" (v));
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    __asm__ volatile ("mov %0 = cr.ivr\n" : "=r" (v));
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    return v;
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}
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/** Write ITC (Interval Timer Counter) register.
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 *
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 * @param New counter value.
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 */
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static inline void itc_write(__u64 v)
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{
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    __asm__ volatile ("mov ar.itc = %0\n" : : "r" (v));
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}
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/** Read ITC (Interval Timer Counter) register.
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 *
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 * @return Current counter value.
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 */
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static inline __u64 itc_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = ar.itc\n" : "=r" (v));
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    return v;
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}
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/** Write ITM (Interval Timer Match) register.
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 *
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 * @param New match value.
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 */
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static inline void itm_write(__u64 v)
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{
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    __asm__ volatile ("mov cr.itm = %0\n" : : "r" (v));
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}
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/** Write ITV (Interval Timer Vector) register.
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 *
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 * @param New vector and masked bit.
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 */
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static inline void itv_write(__u64 v)
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{
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    __asm__ volatile ("mov cr.itv = %0\n" : : "r" (v));
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}
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/** Write EOI (End Of Interrupt) register.
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 *
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 * @param This value is ignored.
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 */
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static inline void eoi_write(__u64 v)
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{
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    __asm__ volatile ("mov cr.eoi = %0\n" : : "r" (v));
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}
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/** Read TPR (Task Priority Register).
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 *
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    return (__u8) (v & 0xf);
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 * @return Current value of TPR.
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 */
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static inline __u64 tpr_read(void)
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{
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    __u64 v;
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    __asm__ volatile ("mov %0 = cr.tpr\n"  : "=r" (v));
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    return v;
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}
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}
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/** Write TPR (Task Priority Register).
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 *
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 * @param New value of TPR.
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 */
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static inline void tpr_write(__u64 v)
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{
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    __asm__ volatile ("mov cr.tpr = %0\n" : : "r" (v));
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}
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/** Disable interrupts.
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 *
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 * Disable interrupts and return previous
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 * value of PSR.
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 *
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 * @return Old interrupt priority level.
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 */
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static ipl_t interrupts_disable(void)
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{
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 144 
    __u64 v;
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    __asm__ volatile (
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        "mov %0 = psr\n"
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        "rsm %1\n"
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        : "=r" (v)
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        : "i" (PSR_I_MASK)
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    );
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    return (ipl_t) v;
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}
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/** Enable interrupts.
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 *
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 * Enable interrupts and return previous
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 * value of PSR.
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 *
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 * @return Old interrupt priority level.
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 */
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void cpu_sleep(void);
 163 
static ipl_t interrupts_enable(void)
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{
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    __u64 v;
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    __asm__ volatile (
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        "mov %0 = psr\n"
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        "ssm %1\n"
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        ";;\n"
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        "srlz.d\n"
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        : "=r" (v)
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        : "i" (PSR_I_MASK)
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    );
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 176 
    return (ipl_t) v;
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}
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/** Restore interrupt priority level.
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 *
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 * Restore PSR.
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 *
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 * @param ipl Saved interrupt priority level.
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 */
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static inline void interrupts_restore(ipl_t ipl)
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{
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void asm_delay_loop(__u32 t);
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    __asm__ volatile (
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        "mov psr.l = %0\n"
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        ";;\n"
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        "srlz.d\n"
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        : : "r" ((__u64) ipl)
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    );
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}
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/** Return interrupt priority level.
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 *
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 * @return PSR.
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 */
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static inline ipl_t interrupts_read(void)
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{
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 201 
    __u64 v;
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    __asm__ volatile ("mov %0 = psr\n" : "=r" (v));
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    return (ipl_t) v;
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}
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#define set_shadow_register(reg,val) {__u64 v = val; __asm__  volatile("mov r15 = %0;;\n""bsw.0;;\n""mov "   #reg   " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); }
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#define set_shadow_register(reg,val) {__u64 v = val; __asm__  volatile("mov r15 = %0;;\n""bsw.0;;\n""mov "   #reg   " = r15;;\n""bsw.1;;\n" : : "r" (v) : "r15" ); }
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#define get_shadow_register(reg,val) {__u64 v ; __asm__  volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
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#define get_shadow_register(reg,val) {__u64 v ; __asm__  volatile("bsw.0;;\n" "mov r15 = r" #reg ";;\n" "bsw.1;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
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#define get_control_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = cr" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
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#define get_control_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = cr" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
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#define get_aplication_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
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#define get_aplication_register(reg,val) {__u64 v ; __asm__  volatile("mov r15 = ar" #reg ";;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
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#define get_psr(val) {__u64 v ; __asm__  volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
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#define get_psr(val) {__u64 v ; __asm__  volatile("mov r15 = psr;;\n" "mov %0 = r15;;\n" : "=r" (v) : : "r15" ); val=v; }
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 - 
 
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void cpu_halt(void);
 215 
extern void cpu_halt(void);
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extern void cpu_sleep(void);
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 217 
extern void asm_delay_loop(__u32 t);
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#endif
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#endif