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34 | * @brief EBUS 'reg' and 'ranges' properties handling. |
34 | * @brief EBUS 'reg' and 'ranges' properties handling. |
35 | * |
35 | * |
36 | */ |
36 | */ |
37 | 37 | ||
38 | #include <genarch/ofw/ofw_tree.h> |
38 | #include <genarch/ofw/ofw_tree.h> |
39 | #include <arch/drivers/pci.h> |
- | |
40 | #include <arch/memstr.h> |
39 | #include <arch/memstr.h> |
41 | #include <arch/trap/interrupt.h> |
40 | #include <arch/trap/interrupt.h> |
42 | #include <func.h> |
41 | #include <func.h> |
43 | #include <panic.h> |
42 | #include <panic.h> |
44 | #include <debug.h> |
43 | #include <debug.h> |
Line 75... | Line 74... | ||
75 | } |
74 | } |
76 | 75 | ||
77 | return false; |
76 | return false; |
78 | } |
77 | } |
79 | 78 | ||
80 | bool ofw_ebus_map_interrupts(ofw_tree_node_t *node, ofw_ebus_reg_t *reg, uint32_t interrupt, int *inr) |
79 | bool ofw_ebus_map_interrupt(ofw_tree_node_t *node, ofw_ebus_reg_t *reg, uint32_t interrupt, int *inr) |
81 | { |
80 | { |
82 | ofw_tree_property_t *prop; |
81 | ofw_tree_property_t *prop; |
83 | ofw_tree_node_t *controller; |
82 | ofw_tree_node_t *controller; |
84 | 83 | ||
85 | prop = ofw_tree_getprop(node, "interrupt-map"); |
84 | prop = ofw_tree_getprop(node, "interrupt-map"); |
Line 112... | Line 111... | ||
112 | return false; |
111 | return false; |
113 | 112 | ||
114 | found: |
113 | found: |
115 | /* |
114 | /* |
116 | * We found the device that functions as an interrupt controller |
115 | * We found the device that functions as an interrupt controller |
117 | * for the interrupt. We also found mapping from interrupt to INR. |
116 | * for the interrupt. We also found partial mapping from interrupt to INO. |
118 | * What needs to be done now is to verify that this indeed is a PCI |
- | |
119 | * node. |
- | |
120 | */ |
117 | */ |
121 | 118 | ||
122 | controller = ofw_tree_find_node_by_handle(ofw_tree_lookup("/"), intr_map[i].controller_handle); |
119 | controller = ofw_tree_find_node_by_handle(ofw_tree_lookup("/"), intr_map[i].controller_handle); |
123 | if (!controller) |
120 | if (!controller) |
124 | return false; |
121 | return false; |
Line 128... | Line 125... | ||
128 | * This is not a PCI node. |
125 | * This is not a PCI node. |
129 | */ |
126 | */ |
130 | return false; |
127 | return false; |
131 | } |
128 | } |
132 | 129 | ||
- | 130 | /* |
|
133 | pci_t *pci = controller->device; |
131 | * Let the PCI do the next step in mapping the interrupt. |
134 | if (!pci) { |
132 | */ |
135 | pci = pci_init(controller); |
133 | if (!ofw_pci_map_interrupt(controller, NULL, intr_map[i].controller_ino, inr)) |
136 | if (!pci) |
- | |
137 | return false; |
134 | return false; |
138 | controller->device = pci; |
- | |
139 | - | ||
140 | } |
- | |
141 | pci_enable_interrupt(pci, intr_map[i].controller_inr); |
- | |
142 | 135 | ||
143 | *inr = intr_map[i].controller_inr; |
- | |
144 | *inr |= 0x1f << IGN_SHIFT; /* 0x1f is hardwired IGN */ |
- | |
145 | - | ||
146 | return true; |
136 | return true; |
147 | } |
137 | } |
148 | 138 | ||
149 | /** @} |
139 | /** @} |
150 | */ |
140 | */ |