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/*
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/*
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 * Copyright (c) 2006 Martin Decky
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 * Copyright (c) 2006 Martin Decky
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 * Copyright (c) 2009 Jiri Svoboda
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 * All rights reserved.
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 * All rights reserved.
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 *
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 *
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 * Redistribution and use in source and binary forms, with or without
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 * Redistribution and use in source and binary forms, with or without
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 * modification, are permitted provided that the following conditions
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 * modification, are permitted provided that the following conditions
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 * are met:
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 * are met:
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#include <console/chardev.h>
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#include <console/chardev.h>
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#include <ddi/irq.h>
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#include <ddi/irq.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <mm/slab.h>
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#include <mm/slab.h>
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#include <ddi/device.h>
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#include <ddi/device.h>
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#include <synch/spinlock.h>
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static void cuda_packet_handle(cuda_instance_t *instance, size_t len);
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/** B register fields */
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enum {
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    TREQ    = 0x08,
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    TACK    = 0x10,
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    TIP = 0x20
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};
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/** IER register fields */
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enum {
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    IER_SET = 0x80,
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    SR_INT  = 0x04
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};
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static irq_ownership_t cuda_claim(irq_t *irq)
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static irq_ownership_t cuda_claim(irq_t *irq)
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{
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{
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    cuda_instance_t *instance = irq->instance;
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    cuda_t *dev = instance->cuda;
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    uint8_t ifr;
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    ifr = pio_read_8(&dev->ifr);
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    if ((ifr & SR_INT) != 0)
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        return IRQ_ACCEPT;
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    else
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    return IRQ_DECLINE;
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        return IRQ_DECLINE;
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}
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}
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static void cuda_irq_handler(irq_t *irq)
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static void cuda_irq_handler(irq_t *irq)
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{
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{
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    cuda_instance_t *instance = irq->instance;
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    cuda_t *dev = instance->cuda;
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    uint8_t b, data;
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    size_t pos;
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    spinlock_lock(&instance->dev_lock);
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    /* We have received one or more CUDA packets. Process them all. */
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    while (true) {
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        b = pio_read_8(&dev->b);
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        if ((b & TREQ) != 0)
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            break;  /* No data */
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        pio_write_8(&dev->b, b & ~TIP);
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        /* Read one packet. */
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        pos = 0;
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        do {
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            data = pio_read_8(&dev->sr);
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            b = pio_read_8(&dev->b);
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            pio_write_8(&dev->b, b ^ TACK);
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            if (pos < CUDA_RCV_BUF_SIZE)
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                instance->rcv_buf[pos++] = data;
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        } while ((b & TREQ) == 0);
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        pio_write_8(&dev->b, b | TACK | TIP);
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        cuda_packet_handle(instance, pos);
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    }
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    spinlock_unlock(&instance->dev_lock);
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}
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static void cuda_packet_handle(cuda_instance_t *instance, size_t len)
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{
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    uint8_t *data = instance->rcv_buf;
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    if (data[0] != 0x00 || data[1] != 0x40 || data[2] != 0x2c)
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        return;
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    /* The packet contains one or two scancodes. */
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    if (data[3] != 0xff)
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        indev_push_character(instance->kbrdin, data[3]);       
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    if (data[4] != 0xff)
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        indev_push_character(instance->kbrdin, data[4]);
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}
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}
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cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
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cuda_instance_t *cuda_init(cuda_t *dev, inr_t inr, cir_t cir, void *cir_arg)
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{
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{
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    cuda_instance_t *instance
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    cuda_instance_t *instance
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        = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
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        = malloc(sizeof(cuda_instance_t), FRAME_ATOMIC);
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    if (instance) {
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    if (instance) {
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        instance->cuda = dev;
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        instance->cuda = dev;
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        instance->kbrdin = NULL;
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        instance->kbrdin = NULL;
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        spinlock_initialize(&instance->dev_lock, "cuda_dev");
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        irq_initialize(&instance->irq);
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        irq_initialize(&instance->irq);
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        instance->irq.devno = device_assign_devno();
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        instance->irq.devno = device_assign_devno();
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        instance->irq.inr = inr;
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        instance->irq.inr = inr;
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        instance->irq.claim = cuda_claim;
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        instance->irq.claim = cuda_claim;
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        instance->irq.handler = cuda_irq_handler;
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        instance->irq.handler = cuda_irq_handler;
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    return instance;
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    return instance;
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}
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}
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void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
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void cuda_wire(cuda_instance_t *instance, indev_t *kbrdin)
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{
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{
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    ASSERT(instance);
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}
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    ASSERT(kbrdin);
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    instance->kbrdin = kbrdin;
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    irq_register(&instance->irq);
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    /* Enable SR interrupt. */
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    pio_write_8(&instance->cuda->ier, IER_SET | SR_INT);
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}
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/** @}
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/** @}
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 */
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 */