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47 | #include <console/cmd.h> |
47 | #include <console/cmd.h> |
48 | #include <console/kconsole.h> |
48 | #include <console/kconsole.h> |
49 | 49 | ||
50 | uintptr_t last_frame = 0; |
50 | uintptr_t last_frame = 0; |
51 | 51 | ||
52 | #define L1_PT_SHIFT 10 |
52 | #define L0_PT_SHIFT 10 |
53 | #define L2_PT_SHIFT 0 |
53 | #define L3_PT_SHIFT 0 |
54 | 54 | ||
55 | #define L1_PT_ENTRIES 1024 |
55 | #define L0_PT_ENTRIES 1024 |
56 | #define L2_PT_ENTRIES 1024 |
56 | #define L3_PT_ENTRIES 1024 |
57 | 57 | ||
58 | #define L1_OFFSET_MASK (L1_PT_ENTRIES - 1) |
58 | #define L0_INDEX_MASK (L0_PT_ENTRIES - 1) |
59 | #define L2_OFFSET_MASK (L2_PT_ENTRIES - 1) |
59 | #define L3_INDEX_MASK (L3_PT_ENTRIES - 1) |
60 | 60 | ||
61 | #define PFN2PTL1_OFFSET(pfn) ((pfn >> L1_PT_SHIFT) & L1_OFFSET_MASK) |
61 | #define PFN2PTL0_INDEX(pfn) ((pfn >> L0_PT_SHIFT) & L0_INDEX_MASK) |
62 | #define PFN2PTL2_OFFSET(pfn) ((pfn >> L2_PT_SHIFT) & L2_OFFSET_MASK) |
62 | #define PFN2PTL3_INDEX(pfn) ((pfn >> L3_PT_SHIFT) & L3_INDEX_MASK) |
63 | 63 | ||
64 | #define PAGE_MASK (~(PAGE_SIZE - 1)) |
64 | #define PAGE_MASK (~(PAGE_SIZE - 1)) |
65 | 65 | ||
66 | #define PTE2ADDR(pte) (pte & PAGE_MASK) |
- | |
67 | - | ||
68 | #define _PAGE_PRESENT 0x001UL |
66 | #define _PAGE_PRESENT 0x001UL |
69 | #define _PAGE_RW 0x002UL |
67 | #define _PAGE_RW 0x002UL |
70 | #define _PAGE_USER 0x004UL |
68 | #define _PAGE_USER 0x004UL |
71 | #define _PAGE_PWT 0x008UL |
69 | #define _PAGE_PWT 0x008UL |
72 | #define _PAGE_PCD 0x010UL |
70 | #define _PAGE_PCD 0x010UL |
Line 74... | Line 72... | ||
74 | #define _PAGE_DIRTY 0x040UL |
72 | #define _PAGE_DIRTY 0x040UL |
75 | #define _PAGE_PAT 0x080UL |
73 | #define _PAGE_PAT 0x080UL |
76 | #define _PAGE_PSE 0x080UL |
74 | #define _PAGE_PSE 0x080UL |
77 | #define _PAGE_GLOBAL 0x100UL |
75 | #define _PAGE_GLOBAL 0x100UL |
78 | 76 | ||
79 | #define L1_PROT (_PAGE_PRESENT | _PAGE_ACCESSED) |
77 | #define L0_PROT (_PAGE_PRESENT | _PAGE_ACCESSED) |
80 | #define L2_PROT (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED) |
78 | #define L3_PROT (_PAGE_PRESENT | _PAGE_RW | _PAGE_ACCESSED) |
81 | 79 | ||
82 | void frame_arch_init(void) |
80 | void frame_arch_init(void) |
83 | { |
81 | { |
84 | if (config.cpu_active == 1) { |
82 | if (config.cpu_active == 1) { |
85 | /* The only memory zone starts just after page table */ |
83 | /* The only memory zone starts just after page table */ |
86 | pfn_t start = ADDR2PFN(ALIGN_UP(KA2PA(start_info.pt_base), PAGE_SIZE)) + start_info.nr_pt_frames; |
84 | pfn_t start = ADDR2PFN(ALIGN_UP(KA2PA(start_info.ptl0), PAGE_SIZE)) + start_info.pt_frames; |
87 | size_t size = start_info.nr_pages - start; |
85 | size_t size = start_info.frames - start; |
88 | 86 | ||
89 | /* Create identity mapping */ |
87 | /* Create identity mapping */ |
90 | pfn_t phys; |
88 | pfn_t phys; |
91 | count_t count = 0; |
89 | count_t count = 0; |
92 | for (phys = start; phys < start + size; phys++) { |
90 | for (phys = start; phys < start + size; phys++) { |
93 | mmu_update_t updates[L2_PT_ENTRIES]; |
91 | mmu_update_t updates[L3_PT_ENTRIES]; |
94 | pfn_t virt = ADDR2PFN(PA2KA(PFN2ADDR(phys))); |
92 | pfn_t virt = ADDR2PFN(PA2KA(PFN2ADDR(phys))); |
95 | 93 | ||
96 | size_t ptl1_offset = PFN2PTL1_OFFSET(virt); |
94 | size_t ptl0_index = PFN2PTL0_INDEX(virt); |
97 | size_t ptl2_offset = PFN2PTL2_OFFSET(virt); |
95 | size_t ptl3_index = PFN2PTL3_INDEX(virt); |
98 | 96 | ||
99 | unsigned long *ptl2_base = (unsigned long *) PTE2ADDR(start_info.pt_base[ptl1_offset]); |
97 | pte_t *ptl3 = (pte_t *) PFN2ADDR(start_info.ptl0[ptl0_index].frame_address); |
100 | 98 | ||
101 | if (ptl2_base == 0) { |
99 | if (ptl3 == 0) { |
102 | mmuext_op_t mmu_ext; |
100 | mmuext_op_t mmu_ext; |
103 | 101 | ||
104 | pfn_t virt2 = ADDR2PFN(PA2KA(PFN2ADDR(start))); |
102 | pfn_t virt2 = ADDR2PFN(PA2KA(PFN2ADDR(start))); |
105 | 103 | ||
106 | /* New L1 page table entry needed */ |
104 | /* New L1 page table entry needed */ |
107 | memsetb(PFN2ADDR(virt2), PAGE_SIZE, 0); |
105 | memsetb(PFN2ADDR(virt2), PAGE_SIZE, 0); |
108 | 106 | ||
109 | size_t ptl1_offset2 = PFN2PTL1_OFFSET(virt2); |
107 | size_t ptl0_index2 = PFN2PTL0_INDEX(virt2); |
110 | size_t ptl2_offset2 = PFN2PTL2_OFFSET(virt2); |
108 | size_t ptl3_index2 = PFN2PTL3_INDEX(virt2); |
111 | unsigned long *ptl2_base2 = (unsigned long *) PTE2ADDR(start_info.pt_base[ptl1_offset2]); |
109 | pte_t *ptl3_2 = (pte_t *) PFN2ADDR(start_info.ptl0[ptl0_index2].frame_address); |
112 | 110 | ||
113 | if (ptl2_base2 == 0) |
111 | if (ptl3_2 == 0) |
114 | panic("Unable to find page table reference"); |
112 | panic("Unable to find page table reference"); |
115 | 113 | ||
116 | updates[count].ptr = (uintptr_t) &ptl2_base2[ptl2_offset2]; |
114 | updates[count].ptr = (uintptr_t) &ptl3_2[ptl3_index2]; |
117 | updates[count].val = PFN2ADDR(start_info.mfn_list[start]) | L1_PROT; |
115 | updates[count].val = PA2MA(PFN2ADDR(start)) | L0_PROT; |
118 | if (xen_mmu_update(updates, count + 1, NULL, DOMID_SELF) < 0) |
116 | if (xen_mmu_update(updates, count + 1, NULL, DOMID_SELF) < 0) |
119 | panic("Unable to map new page table"); |
117 | panic("Unable to map new page table"); |
120 | count = 0; |
118 | count = 0; |
121 | 119 | ||
122 | mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; |
120 | mmu_ext.cmd = MMUEXT_PIN_L1_TABLE; |
123 | mmu_ext.arg1.mfn = start_info.mfn_list[start]; |
121 | mmu_ext.arg1.mfn = ADDR2PFN(PA2MA(PFN2ADDR(start))); |
124 | if (xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) < 0) |
122 | if (xen_mmuext_op(&mmu_ext, 1, NULL, DOMID_SELF) < 0) |
125 | panic("Error pinning new page table"); |
123 | panic("Error pinning new page table"); |
126 | 124 | ||
127 | unsigned long *ptl0 = (unsigned long *) PFN2ADDR(start_info.mfn_list[ADDR2PFN(KA2PA(start_info.pt_base))]); |
125 | pte_t *ptl0 = (pte_t *) PA2MA(KA2PA(start_info.ptl0)); |
128 | 126 | ||
129 | updates[count].ptr = (uintptr_t) &ptl0[ptl1_offset]; |
127 | updates[count].ptr = (uintptr_t) &ptl0[ptl0_index]; |
130 | updates[count].val = PFN2ADDR(start_info.mfn_list[start]) | L2_PROT; |
128 | updates[count].val = PA2MA(PFN2ADDR(start)) | L3_PROT; |
131 | if (xen_mmu_update(updates, count + 1, NULL, DOMID_SELF) < 0) |
129 | if (xen_mmu_update(updates, count + 1, NULL, DOMID_SELF) < 0) |
132 | panic("Unable to update PTE for page table"); |
130 | panic("Unable to update PTE for page table"); |
133 | count = 0; |
131 | count = 0; |
134 | 132 | ||
135 | ptl2_base = (unsigned long *) PTE2ADDR(start_info.pt_base[ptl1_offset]); |
133 | ptl3 = (pte_t *) PFN2ADDR(start_info.ptl0[ptl0_index].frame_address); |
136 | start++; |
134 | start++; |
137 | size--; |
135 | size--; |
138 | } |
136 | } |
139 | 137 | ||
140 | updates[count].ptr = (uintptr_t) &ptl2_base[ptl2_offset]; |
138 | updates[count].ptr = (uintptr_t) &ptl3[ptl3_index]; |
141 | updates[count].val = PFN2ADDR(start_info.mfn_list[phys]) | L2_PROT; |
139 | updates[count].val = PA2MA(PFN2ADDR(phys)) | L3_PROT; |
142 | count++; |
140 | count++; |
143 | 141 | ||
144 | if ((count == L2_PT_ENTRIES) || (phys + 1 == start + size)) { |
142 | if ((count == L3_PT_ENTRIES) || (phys + 1 == start + size)) { |
145 | if (xen_mmu_update(updates, count, NULL, DOMID_SELF) < 0) |
143 | if (xen_mmu_update(updates, count, NULL, DOMID_SELF) < 0) |
146 | panic("Unable to update PTE"); |
144 | panic("Unable to update PTE"); |
147 | count = 0; |
145 | count = 0; |
148 | } |
146 | } |
149 | } |
147 | } |