WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/trap/trap_table.S

 #include <arch/trap/regwin.h>
 #include <arch/trap/interrupt.h>
 #include <arch/trap/exception.h>
 #include <arch/trap/mmu.h>
 #include <arch/stack.h>
+#include <arch/regdef.h>
 #define TABLE_SIZE	TRAP_TABLE_SIZE
 #define ENTRY_SIZE	TRAP_TABLE_ENTRY_SIZE
 /*
 .global fill_0_normal_high
 fill_0_normal_high:
 	FILL_NORMAL_HANDLER
-/* Preemptible trap handler.
+/* Preemptible trap handler for TL=1.
+ *
- * This trap handler makes arrangements to
+ * This trap handler makes arrangements to make calling of scheduler() from
+ * within a trap context possible. It is guaranteed to function only when traps
- * make calling scheduler() possible.
+ * are not nested (i.e. for TL=1).
+ *
+ * Every trap handler on TL=1 that makes a call to the scheduler needs to
+ * be based on this function. The reason behind it is that the nested
+ * trap levels and the automatic saving of the interrupted context by hardware
+ * does not work well together with scheduling (i.e. a thread cannot be rescheduled
+ * with TL>0). Therefore it is necessary to eliminate the effect of trap levels
+ * by software and save the necessary state on the kernel stack.
+ *
+ * Note that for traps with TL>1, more state needs to be saved. This function
+ * is therefore not going to work when TL>1.
+ *
- * The caller is responsible for doing save
+ * The caller is responsible for doing SAVE and allocating
- * and allocating PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE
+ * PREEMPTIBLE_HANDLER_STACK_FRAME_SIZE bytes on the stack.
- * bytes on stack.
+ *
  * Input registers:
  * 	%l0	 	Address of function to call.
  * Output registers:
  *	 %l1 - %l7 	Copy of %g1 - %g7
 	rdpr %tstate, %g1
 	rdpr %tpc, %g2
 	rdpr %tnpc, %g3
 	rdpr %pstate, %g4
+	/*
+	 * The following memory accesses will not fault
+	 * because special provisions are made to have
+	 * the kernel stack of THREAD locked in DTLB.
+	 */
 	stx %g1, [%fp + STACK_BIAS + SAVED_TSTATE]
 	stx %g2, [%fp + STACK_BIAS + SAVED_TPC]
 	stx %g3, [%fp + STACK_BIAS + SAVED_TNPC]
 	stx %g4, [%fp + STACK_BIAS + SAVED_PSTATE]
 	/*
 	 * Alter PSTATE.
 	 * - switch to normal globals.
 	 */
-	and %g4, ~1, %g4		! mask alternate globals
+	and %g4, ~(PSTATE_AG_BIT|PSTATE_IG_BIT|PSTATE_MG_BIT), %g4
 	wrpr %g4, 0, %pstate
 	/*
 	 * Save the normal globals.
 	 */
 	SAVE_GLOBALS
 	/*
 	 * Call the higher-level handler.
 	 */
+	mov %fp, %o1				! calculate istate address
 	call %l0
-	nop
+	add %o1, STACK_BIAS + SAVED_PSTATE, %o1	! calculate istate address
 	/*
-	 * Restore the normal global register set.
+	 * Restore	 the normal global register set.
 	 */
 	RESTORE_GLOBALS
 	/*
 	 * Restore PSTATE from saved copy.
-	 * Alternate globals become active.
+	 * Alternate/Interrupt/MM globals become active.
 	 */
 	ldx [%fp + STACK_BIAS + SAVED_PSTATE], %l4
 	wrpr %l4, 0, %pstate
 	/*
 	 * Do restore to match the save instruction from the top-level handler.
 	 */
 	restore
 	/*
-	 * On execution of retry instruction, CWP will be restored from TSTATE register.
+	 * On execution of the RETRY instruction, CWP will be restored from the TSTATE
-	 * However, because of scheduling, it is possible that CWP in saved TSTATE
+	 * register. However, because of scheduling, it is possible that CWP in the saved
-	 * is different from current CWP. The following chunk of code fixes CWP
+	 * TSTATE is different from the current CWP. The following chunk of code fixes
-	 * in the saved copy of TSTATE.
+	 * CWP in the saved copy of TSTATE.
 	 */
 	rdpr %cwp, %g4		! read current CWP
 	and %g1, ~0x1f, %g1	! clear CWP field in saved TSTATE
 	or %g1, %g4, %g1	! write current CWP to TSTATE

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(root)/trunk/kernel/arch/sparc64/src/trap/trap_table.S @ 2071 – Rev 1787 → 1851