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33 | #include <arch/mm/tlb.h> |
33 | #include <arch/mm/tlb.h> |
34 | #include <arch/mm/tte.h> |
34 | #include <arch/mm/tte.h> |
35 | 35 | ||
36 | .register %g2, #scratch |
36 | .register %g2, #scratch |
37 | .register %g3, #scratch |
37 | .register %g3, #scratch |
38 | .register %g6, #scratch |
- | |
39 | .register %g7, #scratch |
- | |
40 | 38 | ||
41 | .section K_TEXT_START, "ax" |
39 | .section K_TEXT_START, "ax" |
42 | 40 | ||
43 | /* |
41 | /* |
44 | * Here is where the kernel is passed control |
42 | * Here is where the kernel is passed control |
Line 151... | Line 149... | ||
151 | * Moreover, the IMMU requires use of the FLUSH instructions. |
149 | * Moreover, the IMMU requires use of the FLUSH instructions. |
152 | * But that is OK because we always use operands with |
150 | * But that is OK because we always use operands with |
153 | * addresses already mapped by the taken over DTLB. |
151 | * addresses already mapped by the taken over DTLB. |
154 | */ |
152 | */ |
155 | 153 | ||
156 | set kernel_image_start, %g7 |
154 | set kernel_image_start, %g5 |
157 | 155 | ||
158 | ! write ITLB tag of context 1 |
156 | ! write ITLB tag of context 1 |
159 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
157 | SET_TLB_TAG(g1, MEM_CONTEXT_TEMP) |
160 | set VA_DMMU_TAG_ACCESS, %g2 |
158 | set VA_DMMU_TAG_ACCESS, %g2 |
161 | stxa %g1, [%g2] ASI_IMMU |
159 | stxa %g1, [%g2] ASI_IMMU |
162 | flush %g7 |
160 | flush %g5 |
163 | 161 | ||
164 | ! write ITLB data and install the temporary mapping in context 1 |
162 | ! write ITLB data and install the temporary mapping in context 1 |
165 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
163 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
166 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
164 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
167 | flush %g7 |
165 | flush %g5 |
168 | 166 | ||
169 | ! switch to context 1 |
167 | ! switch to context 1 |
170 | set MEM_CONTEXT_TEMP, %g1 |
168 | set MEM_CONTEXT_TEMP, %g1 |
171 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
169 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
172 | flush %g7 |
170 | flush %g5 |
173 | 171 | ||
174 | ! demap context 0 |
172 | ! demap context 0 |
175 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
173 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_NUCLEUS) |
176 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
174 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
177 | flush %g7 |
175 | flush %g5 |
178 | 176 | ||
179 | ! write ITLB tag of context 0 |
177 | ! write ITLB tag of context 0 |
180 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
178 | SET_TLB_TAG(g1, MEM_CONTEXT_KERNEL) |
181 | set VA_DMMU_TAG_ACCESS, %g2 |
179 | set VA_DMMU_TAG_ACCESS, %g2 |
182 | stxa %g1, [%g2] ASI_IMMU |
180 | stxa %g1, [%g2] ASI_IMMU |
183 | flush %g7 |
181 | flush %g5 |
184 | 182 | ||
185 | ! write ITLB data and install the permanent kernel mapping in context 0 |
183 | ! write ITLB data and install the permanent kernel mapping in context 0 |
186 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
184 | SET_TLB_DATA(g1, g2, 0) ! use non-global mapping |
187 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
185 | stxa %g1, [%g0] ASI_ITLB_DATA_IN_REG |
188 | flush %g7 |
186 | flush %g5 |
189 | 187 | ||
190 | ! switch to context 0 |
188 | ! switch to context 0 |
191 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
189 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
192 | flush %g7 |
190 | flush %g5 |
193 | 191 | ||
194 | ! ensure nucleus mapping |
192 | ! ensure nucleus mapping |
195 | wrpr %g0, 1, %tl |
193 | wrpr %g0, 1, %tl |
196 | 194 | ||
197 | ! set context 1 in the primary context register |
195 | ! set context 1 in the primary context register |
198 | set MEM_CONTEXT_TEMP, %g1 |
196 | set MEM_CONTEXT_TEMP, %g1 |
199 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
197 | stxa %g1, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
200 | flush %g7 |
198 | flush %g5 |
201 | 199 | ||
202 | ! demap context 1 |
200 | ! demap context 1 |
203 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
201 | SET_TLB_DEMAP_CMD(g1, TLB_DEMAP_PRIMARY) |
204 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
202 | stxa %g0, [%g1] ASI_IMMU_DEMAP |
205 | flush %g7 |
203 | flush %g5 |
206 | 204 | ||
207 | ! set context 0 in the primary context register |
205 | ! set context 0 in the primary context register |
208 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
206 | stxa %g0, [VA_PRIMARY_CONTEXT_REG] %asi ! ASI_DMMU is correct here !!! |
209 | flush %g7 |
207 | flush %g5 |
210 | 208 | ||
211 | ! set TL back to 0 |
209 | ! set TL back to 0 |
212 | wrpr %g0, 0, %tl |
210 | wrpr %g0, 0, %tl |
213 | 211 | ||
214 | call main_bsp |
212 | call main_bsp |