WebSVN – HelenOS – Diff – /trunk/kernel/arch/sparc64/src/mm/tsb.c



 * Note that respective portions of both TSBs
 * are invalidated at a time.
 *
 * @param as Address space.
 * @param page First page to invalidate in TSB.
 * @param pages Number of pages to invalidate.
 *      Value of (count_t) -1 means the whole TSB.
 */
void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
{
    index_t i0, i;
    count_t cnt;

   
    i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK;
    cnt = min(pages, ITSB_ENTRY_COUNT);
   
    for (i = 0; i < cnt; i++) {
        as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = true;
        as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = true;
    }
}
 
/** Copy software PTE to ITSB.
 *

     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will
     * be repeated.
     */
 
    tsb->tag.invalid = true;    /* invalidate the entry
                     * (tag target has this
                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = t->frame >> PAGE_WIDTH;
    tsb->data.cp = t->c;
    tsb->data.cv = t->c;
    tsb->data.p = t->k;     /* p as privileged */
    tsb->data.v = t->p;
   
    write_barrier();
   
    tsb->tag.invalid = false;   /* mark the entry as valid */
}
 
/** Copy software PTE to DTSB.
 *
 * @param t Software PTE.

     * We use write barriers to make sure that the TSB load
     * won't use inconsistent data or that the fault will
     * be repeated.
     */
 
    tsb->tag.invalid = true;    /* invalidate the entry
                     * (tag target has this
                     * set to 0) */
 
    write_barrier();
 
    tsb->tag.context = as->asid;
    tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
    tsb->data.value = 0;
    tsb->data.size = PAGESIZE_8K;
    tsb->data.pfn = t->frame >> PAGE_WIDTH;
    tsb->data.cp = t->c;
    tsb->data.cv = t->c;
    tsb->data.p = t->k;     /* p as privileged */
    tsb->data.w = ro ? false : t->w;
    tsb->data.v = t->p;
   
    write_barrier();
   
    tsb->tag.invalid = true;    /* mark the entry as valid */
}
 
/** @}
 */

Rev 1917	Rev 1960
Line 49...	Line 49...
49	* Note that respective portions of both TSBs	49	* Note that respective portions of both TSBs
50	* are invalidated at a time.	50	* are invalidated at a time.
51	*	51	*
52	* @param as Address space.	52	* @param as Address space.
53	* @param page First page to invalidate in TSB.	53	* @param page First page to invalidate in TSB.
54	* @param pages Number of pages to invalidate. Value of (count_t) -1 means the whole TSB.	54	* @param pages Number of pages to invalidate.
-		55	* Value of (count_t) -1 means the whole TSB.
55	*/	56	*/
56	void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)	57	void tsb_invalidate(as_t *as, uintptr_t page, count_t pages)
57	{	58	{
58	index_t i0, i;	59	index_t i0, i;
59	count_t cnt;	60	count_t cnt;
Line 62...	Line 63...
62		63
63	i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK;	64	i0 = (page >> PAGE_WIDTH) & TSB_INDEX_MASK;
64	cnt = min(pages, ITSB_ENTRY_COUNT);	65	cnt = min(pages, ITSB_ENTRY_COUNT);
65		66
66	for (i = 0; i < cnt; i++) {	67	for (i = 0; i < cnt; i++) {
67	as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = 0;	68	as->arch.itsb[(i0 + i) & (ITSB_ENTRY_COUNT-1)].tag.invalid = true;
68	as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = 0;	69	as->arch.dtsb[(i0 + i) & (DTSB_ENTRY_COUNT-1)].tag.invalid = true;
69	}	70	}
70	}	71	}
71		72
72	/** Copy software PTE to ITSB.	73	/** Copy software PTE to ITSB.
73	*	74	*
Line 85...	Line 86...
85	* We use write barriers to make sure that the TSB load	86	* We use write barriers to make sure that the TSB load
86	* won't use inconsistent data or that the fault will	87	* won't use inconsistent data or that the fault will
87	* be repeated.	88	* be repeated.
88	*/	89	*/
89		90
90	tsb->tag.invalid = 1; /* invalidate the entry (tag target has this set to 0) */	91	tsb->tag.invalid = true; /* invalidate the entry
-		92	* (tag target has this
-		93	* set to 0) */
91		94
92	write_barrier();	95	write_barrier();
93		96
94	tsb->tag.context = as->asid;	97	tsb->tag.context = as->asid;
95	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;	98	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
96	tsb->data.value = 0;	99	tsb->data.value = 0;
97	tsb->data.size = PAGESIZE_8K;	100	tsb->data.size = PAGESIZE_8K;
98	tsb->data.pfn = t->frame >> PAGE_WIDTH;	101	tsb->data.pfn = t->frame >> PAGE_WIDTH;
99	tsb->data.cp = t->c;	102	tsb->data.cp = t->c;
100	tsb->data.cv = t->c;	103	tsb->data.cv = t->c;
101	tsb->data.p = t->k; /* p as privileged */	104	tsb->data.p = t->k; /* p as privileged */
102	tsb->data.v = t->p;	105	tsb->data.v = t->p;
103		106
104	write_barrier();	107	write_barrier();
105		108
106	tsb->tag.invalid = 0; /* mark the entry as valid */	109	tsb->tag.invalid = false; /* mark the entry as valid */
107	}	110	}
108		111
109	/** Copy software PTE to DTSB.	112	/** Copy software PTE to DTSB.
110	*	113	*
111	* @param t Software PTE.	114	* @param t Software PTE.
Line 123...	Line 126...
123	* We use write barriers to make sure that the TSB load	126	* We use write barriers to make sure that the TSB load
124	* won't use inconsistent data or that the fault will	127	* won't use inconsistent data or that the fault will
125	* be repeated.	128	* be repeated.
126	*/	129	*/
127		130
128	tsb->tag.invalid = 1; /* invalidate the entry (tag target has this set to 0) */	131	tsb->tag.invalid = true; /* invalidate the entry
-		132	* (tag target has this
-		133	* set to 0) */
129		134
130	write_barrier();	135	write_barrier();
131		136
132	tsb->tag.context = as->asid;	137	tsb->tag.context = as->asid;
133	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;	138	tsb->tag.va_tag = t->page >> VA_TAG_PAGE_SHIFT;
134	tsb->data.value = 0;	139	tsb->data.value = 0;
135	tsb->data.size = PAGESIZE_8K;	140	tsb->data.size = PAGESIZE_8K;
136	tsb->data.pfn = t->frame >> PAGE_WIDTH;	141	tsb->data.pfn = t->frame >> PAGE_WIDTH;
137	tsb->data.cp = t->c;	142	tsb->data.cp = t->c;
138	tsb->data.cv = t->c;	143	tsb->data.cv = t->c;
139	tsb->data.p = t->k; /* p as privileged */	144	tsb->data.p = t->k; /* p as privileged */
140	tsb->data.w = ro ? false : t->w;	145	tsb->data.w = ro ? false : t->w;
141	tsb->data.v = t->p;	146	tsb->data.v = t->p;
142		147
143	write_barrier();	148	write_barrier();
144		149
145	tsb->tag.invalid = 0; /* mark the entry as valid */	150	tsb->tag.invalid = true; /* mark the entry as valid */
146	}	151	}
147		152
148	/** @}	153	/** @}
149	*/	154	*/

Subversion Repositories HelenOS

(root)/trunk/kernel/arch/sparc64/src/mm/tsb.c @ 1962 – Rev 1917 → 1960