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Line 196... | Line 196... | ||
196 | 196 | ||
197 | itlb_data_in_write(data.value); |
197 | itlb_data_in_write(data.value); |
198 | } |
198 | } |
199 | 199 | ||
200 | /** ITLB miss handler. */ |
200 | /** ITLB miss handler. */ |
201 | void fast_instruction_access_mmu_miss(int n, istate_t *istate) |
201 | void fast_instruction_access_mmu_miss(unative_t unused, istate_t *istate) |
202 | { |
202 | { |
203 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
203 | uintptr_t va = ALIGN_DOWN(istate->tpc, PAGE_SIZE); |
204 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
204 | index_t index = (istate->tpc >> MMU_PAGE_WIDTH) % MMU_PAGES_PER_PAGE; |
205 | pte_t *t; |
205 | pte_t *t; |
206 | 206 | ||
Line 232... | Line 232... | ||
232 | 232 | ||
233 | /** DTLB miss handler. |
233 | /** DTLB miss handler. |
234 | * |
234 | * |
235 | * Note that some faults (e.g. kernel faults) were already resolved by the |
235 | * Note that some faults (e.g. kernel faults) were already resolved by the |
236 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
236 | * low-level, assembly language part of the fast_data_access_mmu_miss handler. |
- | 237 | * |
|
- | 238 | * @param tag Content of the TLB Tag Access register as it existed when the |
|
- | 239 | * trap happened. This is to prevent confusion created by clobbered |
|
- | 240 | * Tag Access register during a nested DTLB miss. |
|
- | 241 | * @param istate Interrupted state saved on the stack. |
|
237 | */ |
242 | */ |
238 | void fast_data_access_mmu_miss(int n, istate_t *istate) |
243 | void fast_data_access_mmu_miss(tlb_tag_access_reg_t tag, istate_t *istate) |
239 | { |
244 | { |
240 | tlb_tag_access_reg_t tag; |
- | |
241 | uintptr_t va; |
245 | uintptr_t va; |
242 | index_t index; |
246 | index_t index; |
243 | pte_t *t; |
247 | pte_t *t; |
244 | 248 | ||
245 | tag.value = dtlb_tag_access_read(); |
- | |
246 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
249 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
247 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
250 | index = tag.vpn % MMU_PAGES_PER_PAGE; |
248 | 251 | ||
249 | if (tag.context == ASID_KERNEL) { |
252 | if (tag.context == ASID_KERNEL) { |
250 | if (!tag.vpn) { |
253 | if (!tag.vpn) { |
Line 280... | Line 283... | ||
280 | __FUNCTION__); |
283 | __FUNCTION__); |
281 | } |
284 | } |
282 | } |
285 | } |
283 | } |
286 | } |
284 | 287 | ||
285 | /** DTLB protection fault handler. */ |
288 | /** DTLB protection fault handler. |
- | 289 | * |
|
- | 290 | * @param tag Content of the TLB Tag Access register as it existed when the |
|
- | 291 | * trap happened. This is to prevent confusion created by clobbered |
|
- | 292 | * Tag Access register during a nested DTLB miss. |
|
- | 293 | * @param istate Interrupted state saved on the stack. |
|
- | 294 | */ |
|
286 | void fast_data_access_protection(int n, istate_t *istate) |
295 | void fast_data_access_protection(tlb_tag_access_reg_t tag, istate_t *istate) |
287 | { |
296 | { |
288 | tlb_tag_access_reg_t tag; |
- | |
289 | uintptr_t va; |
297 | uintptr_t va; |
290 | index_t index; |
298 | index_t index; |
291 | pte_t *t; |
299 | pte_t *t; |
292 | 300 | ||
293 | tag.value = dtlb_tag_access_read(); |
- | |
294 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
301 | va = ALIGN_DOWN((uint64_t) tag.vpn << MMU_PAGE_WIDTH, PAGE_SIZE); |
295 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
302 | index = tag.vpn % MMU_PAGES_PER_PAGE; /* 16K-page emulation */ |
296 | 303 | ||
297 | page_table_lock(AS, true); |
304 | page_table_lock(AS, true); |
298 | t = page_mapping_find(AS, va); |
305 | t = page_mapping_find(AS, va); |
Line 369... | Line 376... | ||
369 | tlb_tag_access_reg_t tag, const char *str) |
376 | tlb_tag_access_reg_t tag, const char *str) |
370 | { |
377 | { |
371 | uintptr_t va; |
378 | uintptr_t va; |
372 | 379 | ||
373 | va = tag.vpn << MMU_PAGE_WIDTH; |
380 | va = tag.vpn << MMU_PAGE_WIDTH; |
374 | - | ||
- | 381 | if (tag.context) { |
|
375 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
382 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
376 | tag.context); |
383 | tag.context); |
- | 384 | } |
|
377 | dump_istate(istate); |
385 | dump_istate(istate); |
378 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
386 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
379 | panic("%s\n", str); |
387 | panic("%s\n", str); |
380 | } |
388 | } |
381 | 389 | ||
Line 384... | Line 392... | ||
384 | { |
392 | { |
385 | uintptr_t va; |
393 | uintptr_t va; |
386 | 394 | ||
387 | va = tag.vpn << MMU_PAGE_WIDTH; |
395 | va = tag.vpn << MMU_PAGE_WIDTH; |
388 | 396 | ||
- | 397 | if (tag.context) { |
|
389 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
398 | fault_if_from_uspace(istate, "%s, Page=%p (ASID=%d)\n", str, va, |
390 | tag.context); |
399 | tag.context); |
- | 400 | } |
|
391 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
401 | printf("Faulting page: %p, ASID=%d\n", va, tag.context); |
392 | dump_istate(istate); |
402 | dump_istate(istate); |
393 | panic("%s\n", str); |
403 | panic("%s\n", str); |
394 | } |
404 | } |
395 | 405 |