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Rev 2015 | Rev 2048 | ||
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Line 59... | Line 59... | ||
59 | } |
59 | } |
60 | 60 | ||
61 | int as_constructor_arch(as_t *as, int flags) |
61 | int as_constructor_arch(as_t *as, int flags) |
62 | { |
62 | { |
63 | #ifdef CONFIG_TSB |
63 | #ifdef CONFIG_TSB |
64 | int order = fnzb32(((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH); |
64 | int order = fnzb32(((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
- | 65 | sizeof(tsb_entry_t)) >> FRAME_WIDTH); |
|
65 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
66 | uintptr_t tsb = (uintptr_t) frame_alloc(order, flags | FRAME_KA); |
66 | 67 | ||
67 | if (!tsb) |
68 | if (!tsb) |
68 | return -1; |
69 | return -1; |
69 | 70 | ||
70 | as->arch.itsb = (tsb_entry_t *) tsb; |
71 | as->arch.itsb = (tsb_entry_t *) tsb; |
71 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * sizeof(tsb_entry_t)); |
72 | as->arch.dtsb = (tsb_entry_t *) (tsb + ITSB_ENTRY_COUNT * |
- | 73 | sizeof(tsb_entry_t)); |
|
72 | memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t), 0); |
74 | memsetb((uintptr_t) as->arch.itsb, (ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) |
- | 75 | * sizeof(tsb_entry_t), 0); |
|
73 | #endif |
76 | #endif |
74 | return 0; |
77 | return 0; |
75 | } |
78 | } |
76 | 79 | ||
77 | int as_destructor_arch(as_t *as) |
80 | int as_destructor_arch(as_t *as) |
78 | { |
81 | { |
79 | #ifdef CONFIG_TSB |
82 | #ifdef CONFIG_TSB |
80 | count_t cnt = ((ITSB_ENTRY_COUNT+DTSB_ENTRY_COUNT)*sizeof(tsb_entry_t))>>FRAME_WIDTH; |
83 | count_t cnt = ((ITSB_ENTRY_COUNT + DTSB_ENTRY_COUNT) * |
- | 84 | sizeof(tsb_entry_t)) >> FRAME_WIDTH; |
|
81 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
85 | frame_free(KA2PA((uintptr_t) as->arch.itsb)); |
82 | return cnt; |
86 | return cnt; |
83 | #else |
87 | #else |
84 | return 0; |
88 | return 0; |
85 | #endif |
89 | #endif |
Line 97... | Line 101... | ||
97 | interrupts_restore(ipl); |
101 | interrupts_restore(ipl); |
98 | #endif |
102 | #endif |
99 | return 0; |
103 | return 0; |
100 | } |
104 | } |
101 | 105 | ||
102 | /** Perform sparc64-specific tasks when an address space becomes active on the processor. |
106 | /** Perform sparc64-specific tasks when an address space becomes active on the |
- | 107 | * processor. |
|
103 | * |
108 | * |
104 | * Install ASID and map TSBs. |
109 | * Install ASID and map TSBs. |
105 | * |
110 | * |
106 | * @param as Address space. |
111 | * @param as Address space. |
107 | */ |
112 | */ |
Line 132... | Line 137... | ||
132 | 137 | ||
133 | ASSERT(as->arch.itsb && as->arch.dtsb); |
138 | ASSERT(as->arch.itsb && as->arch.dtsb); |
134 | 139 | ||
135 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
140 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
136 | 141 | ||
137 | if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
142 | if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
138 | /* |
143 | /* |
139 | * TSBs were allocated from memory not covered |
144 | * TSBs were allocated from memory not covered |
140 | * by the locked 4M kernel DTLB entry. We need |
145 | * by the locked 4M kernel DTLB entry. We need |
141 | * to map both TSBs explicitly. |
146 | * to map both TSBs explicitly. |
142 | */ |
147 | */ |
Line 158... | Line 163... | ||
158 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH; |
163 | tsb_base.base = ((uintptr_t) as->arch.dtsb) >> PAGE_WIDTH; |
159 | dtsb_base_write(tsb_base.value); |
164 | dtsb_base_write(tsb_base.value); |
160 | #endif |
165 | #endif |
161 | } |
166 | } |
162 | 167 | ||
163 | /** Perform sparc64-specific tasks when an address space is removed from the processor. |
168 | /** Perform sparc64-specific tasks when an address space is removed from the |
- | 169 | * processor. |
|
164 | * |
170 | * |
165 | * Demap TSBs. |
171 | * Demap TSBs. |
166 | * |
172 | * |
167 | * @param as Address space. |
173 | * @param as Address space. |
168 | */ |
174 | */ |
Line 181... | Line 187... | ||
181 | 187 | ||
182 | ASSERT(as->arch.itsb && as->arch.dtsb); |
188 | ASSERT(as->arch.itsb && as->arch.dtsb); |
183 | 189 | ||
184 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
190 | uintptr_t tsb = (uintptr_t) as->arch.itsb; |
185 | 191 | ||
186 | if (!overlaps(tsb, 8*PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
192 | if (!overlaps(tsb, 8 * PAGE_SIZE, base, 1 << KERNEL_PAGE_WIDTH)) { |
187 | /* |
193 | /* |
188 | * TSBs were allocated from memory not covered |
194 | * TSBs were allocated from memory not covered |
189 | * by the locked 4M kernel DTLB entry. We need |
195 | * by the locked 4M kernel DTLB entry. We need |
190 | * to demap the entry installed by as_install_arch(). |
196 | * to demap the entry installed by as_install_arch(). |
191 | */ |
197 | */ |