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28 | 28 | ||
29 | #ifndef __sparc64_TLB_H__ |
29 | #ifndef __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
30 | #define __sparc64_TLB_H__ |
31 | 31 | ||
32 | #include <arch/mm/tte.h> |
32 | #include <arch/mm/tte.h> |
- | 33 | #include <arch/mm/page.h> |
|
33 | #include <arch/asm.h> |
34 | #include <arch/asm.h> |
34 | #include <arch/barrier.h> |
35 | #include <arch/barrier.h> |
35 | #include <arch/types.h> |
36 | #include <arch/types.h> |
36 | #include <typedefs.h> |
37 | #include <typedefs.h> |
37 | 38 | ||
Line 91... | Line 92... | ||
91 | 92 | ||
92 | /** I-/D-TLB Tag Read Register. */ |
93 | /** I-/D-TLB Tag Read Register. */ |
93 | union tlb_tag_read_reg { |
94 | union tlb_tag_read_reg { |
94 | __u64 value; |
95 | __u64 value; |
95 | struct { |
96 | struct { |
96 | __u64 va : 51; /**< Virtual Address. */ |
97 | __u64 vpn : 51; /**< Virtual Address bits 63:13. */ |
97 | unsigned context : 13; /**< Context identifier. */ |
98 | unsigned context : 13; /**< Context identifier. */ |
98 | } __attribute__ ((packed)); |
99 | } __attribute__ ((packed)); |
99 | }; |
100 | }; |
100 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
101 | typedef union tlb_tag_read_reg tlb_tag_read_reg_t; |
101 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
102 | typedef union tlb_tag_read_reg tlb_tag_access_reg_t; |
102 | 103 | ||
- | 104 | /** TLB Demap Operation types. */ |
|
- | 105 | #define TLB_DEMAP_PAGE 0 |
|
- | 106 | #define TLB_DEMAP_CONTEXT 1 |
|
- | 107 | ||
- | 108 | /** TLB Demap Operation Context register encodings. */ |
|
- | 109 | #define TLB_DEMAP_PRIMARY 0 |
|
- | 110 | #define TLB_DEMAP_SECONDARY 1 |
|
- | 111 | #define TLB_DEMAP_NUCLEUS 2 |
|
- | 112 | ||
- | 113 | /** TLB Demap Operation Address. */ |
|
- | 114 | union tlb_demap_addr { |
|
- | 115 | __u64 value; |
|
- | 116 | struct { |
|
- | 117 | __u64 vpn: 51; /**< Virtual Address bits 63:13. */ |
|
- | 118 | unsigned : 6; /**< Ignored. */ |
|
- | 119 | unsigned type : 1; /**< The type of demap operation. */ |
|
- | 120 | unsigned context : 2; /**< Context register selection. */ |
|
- | 121 | unsigned : 4; /**< Zero. */ |
|
- | 122 | } __attribute__ ((packed)); |
|
- | 123 | }; |
|
- | 124 | typedef union tlb_demap_addr tlb_demap_addr_t; |
|
- | 125 | ||
103 | /** Read IMMU TLB Data Access Register. |
126 | /** Read IMMU TLB Data Access Register. |
104 | * |
127 | * |
105 | * @param entry TLB Entry index. |
128 | * @param entry TLB Entry index. |
106 | * |
129 | * |
107 | * @return Current value of specified IMMU TLB Data Access Register. |
130 | * @return Current value of specified IMMU TLB Data Access Register. |
Line 113... | Line 136... | ||
113 | reg.value = 0; |
136 | reg.value = 0; |
114 | reg.tlb_entry = entry; |
137 | reg.tlb_entry = entry; |
115 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
138 | return asi_u64_read(ASI_ITLB_DATA_ACCESS_REG, reg.value); |
116 | } |
139 | } |
117 | 140 | ||
- | 141 | /** Write IMMU TLB Data Access Register. |
|
- | 142 | * |
|
- | 143 | * @param entry TLB Entry index. |
|
- | 144 | * @param value Value to be written. |
|
- | 145 | */ |
|
- | 146 | static inline __u64 itlb_data_access_write(index_t entry, __u64 value) |
|
- | 147 | { |
|
- | 148 | tlb_data_access_addr_t reg; |
|
- | 149 | ||
- | 150 | reg.value = 0; |
|
- | 151 | reg.tlb_entry = entry; |
|
- | 152 | asi_u64_write(ASI_ITLB_DATA_ACCESS_REG, reg.value, value); |
|
- | 153 | flush(); |
|
- | 154 | } |
|
- | 155 | ||
118 | /** Read DMMU TLB Data Access Register. |
156 | /** Read DMMU TLB Data Access Register. |
119 | * |
157 | * |
120 | * @param entry TLB Entry index. |
158 | * @param entry TLB Entry index. |
121 | * |
159 | * |
122 | * @return Current value of specified DMMU TLB Data Access Register. |
160 | * @return Current value of specified DMMU TLB Data Access Register. |
Line 128... | Line 166... | ||
128 | reg.value = 0; |
166 | reg.value = 0; |
129 | reg.tlb_entry = entry; |
167 | reg.tlb_entry = entry; |
130 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
168 | return asi_u64_read(ASI_DTLB_DATA_ACCESS_REG, reg.value); |
131 | } |
169 | } |
132 | 170 | ||
- | 171 | /** Write DMMU TLB Data Access Register. |
|
- | 172 | * |
|
- | 173 | * @param entry TLB Entry index. |
|
- | 174 | * @param value Value to be written. |
|
- | 175 | */ |
|
- | 176 | static inline __u64 dtlb_data_access_write(index_t entry, __u64 value) |
|
- | 177 | { |
|
- | 178 | tlb_data_access_addr_t reg; |
|
- | 179 | ||
- | 180 | reg.value = 0; |
|
- | 181 | reg.tlb_entry = entry; |
|
- | 182 | asi_u64_write(ASI_DTLB_DATA_ACCESS_REG, reg.value, value); |
|
- | 183 | flush(); |
|
- | 184 | } |
|
- | 185 | ||
133 | /** Read IMMU TLB Tag Read Register. |
186 | /** Read IMMU TLB Tag Read Register. |
134 | * |
187 | * |
135 | * @param entry TLB Entry index. |
188 | * @param entry TLB Entry index. |
136 | * |
189 | * |
137 | * @return Current value of specified IMMU TLB Tag Read Register. |
190 | * @return Current value of specified IMMU TLB Tag Read Register. |
Line 198... | Line 251... | ||
198 | { |
251 | { |
199 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
252 | asi_u64_write(ASI_DTLB_DATA_IN_REG, 0, v); |
200 | flush(); |
253 | flush(); |
201 | } |
254 | } |
202 | 255 | ||
- | 256 | /** Perform IMMU TLB Demap Operation. |
|
- | 257 | * |
|
- | 258 | * @param type Selects between context and page demap. |
|
- | 259 | * @param context_encoding Specifies which Context register has Context ID for demap. |
|
- | 260 | * @param page Address which is on the page to be demapped. |
|
- | 261 | */ |
|
- | 262 | static inline void itlb_demap(int type, int context_encoding, __address page) |
|
- | 263 | { |
|
- | 264 | tlb_demap_addr_t da; |
|
- | 265 | page_address_t pg; |
|
- | 266 | ||
- | 267 | da.value = 0; |
|
- | 268 | pg.address = page; |
|
- | 269 | ||
- | 270 | da.type = type; |
|
- | 271 | da.context = context_encoding; |
|
- | 272 | da.vpn = pg.vpn; |
|
- | 273 | ||
- | 274 | asi_u64_write(ASI_IMMU_DEMAP, da.value, 0); |
|
- | 275 | flush(); |
|
- | 276 | } |
|
- | 277 | ||
- | 278 | /** Perform DMMU TLB Demap Operation. |
|
- | 279 | * |
|
- | 280 | * @param type Selects between context and page demap. |
|
- | 281 | * @param context_encoding Specifies which Context register has Context ID for demap. |
|
- | 282 | * @param page Address which is on the page to be demapped. |
|
- | 283 | */ |
|
- | 284 | static inline void dtlb_demap(int type, int context_encoding, __address page) |
|
- | 285 | { |
|
- | 286 | tlb_demap_addr_t da; |
|
- | 287 | page_address_t pg; |
|
- | 288 | ||
- | 289 | da.value = 0; |
|
- | 290 | pg.address = page; |
|
- | 291 | ||
- | 292 | da.type = type; |
|
- | 293 | da.context = context_encoding; |
|
- | 294 | da.vpn = pg.vpn; |
|
- | 295 | ||
- | 296 | asi_u64_write(ASI_DMMU_DEMAP, da.value, 0); |
|
- | 297 | flush(); |
|
- | 298 | } |
|
- | 299 | ||
203 | #endif |
300 | #endif |