Subversion Repositories HelenOS

Rev

Rev 1842 | Go to most recent revision | Show entire file | Ignore whitespace | Details | Blame | Last modification | View Log | RSS feed

Rev 1842 Rev 1848
Line 34... Line 34...
34 
 
 34 
 
35 
#ifndef KERN_sparc64_Z8530_H_
 35 
#ifndef KERN_sparc64_Z8530_H_
36 
#define KERN_sparc64_Z8530_H_
 36 
#define KERN_sparc64_Z8530_H_
37 
 
 37 
 
38 
#include <arch/types.h>
 38 
#include <arch/types.h>
- 
 
 39 
#include <typedefs.h>
39 
#include <arch/drivers/kbd.h>
 40 
#include <arch/drivers/kbd.h>
40 
 
 41 
 
41 
#define STATUS_REG  4
 - 
 
42 
#define COMMAND_REG 4
 42 
#define Z8530_CHAN_A    4
43 
#define DATA_REG    6
 43 
#define Z8530_CHAN_B    0
44 
 
 44 
 
- 
 
 45 
#define WR0 0
- 
 
 46 
#define WR1 1
- 
 
 47 
#define WR2 2
- 
 
 48 
#define WR3 3
- 
 
 49 
#define WR4 4
- 
 
 50 
#define WR5 5
- 
 
 51 
#define WR6 6
- 
 
 52 
#define WR7 7
- 
 
 53 
#define WR8 8
- 
 
 54 
#define WR9 9
- 
 
 55 
#define WR10    10
- 
 
 56 
#define WR11    11
- 
 
 57 
#define WR12    12
- 
 
 58 
#define WR13    13
45 
#define LAST_REG    DATA_REG
 59 
#define WR14    14
- 
 
 60 
#define WR15    15
- 
 
 61 
 
- 
 
 62 
#define RR0 0
- 
 
 63 
#define RR1 1
- 
 
 64 
#define RR2 2
- 
 
 65 
#define RR3 3
- 
 
 66 
#define RR8 8
- 
 
 67 
#define RR10    10
- 
 
 68 
#define RR12    12
- 
 
 69 
#define RR13    13
- 
 
 70 
#define RR14    14
- 
 
 71 
#define RR15    15
- 
 
 72 
 
- 
 
 73 
/* Write Register 1 */
- 
 
 74 
#define WR1_RID     (0x0<<3)    /** Receive Interrupts Disabled. */
- 
 
 75 
#define WR1_RIFCSC  (0x1<<3)    /** Receive Interrupt on First Character or Special Condition. */
- 
 
 76 
#define WR1_IARCSC  (0x2<<3)    /** Interrupt on All Receive Characters or Special Conditions. */
- 
 
 77 
#define WR1_RISC    (0x3<<3)    /** Receive Interrupt on Special Condition. */
- 
 
 78 
#define WR1_PISC    (0x1<<2)    /** Parity Is Special Condition. */
- 
 
 79 
 
- 
 
 80 
/* Write Register 3 */
- 
 
 81 
#define WR3_RX_ENABLE   (0x1<<0)    /** Rx Enable. */
- 
 
 82 
#define WR3_RX8BITSCH   (0x3<<6)    /** 8-bits per character. */
46 
 
 83 
 
- 
 
 84 
/* Write Register 9 */
- 
 
 85 
#define WR9_MIE     (0x1<<3)    /** Master Interrupt Enable. */
- 
 
 86 
 
- 
 
 87 
/* Read Register 0 */
- 
 
 88 
#define RR0_RCA     (0x1<<0)    /** Receive Character Available. */
- 
 
 89 
 
47 
static inline void z8530_data_write(uint8_t data)
 90 
static inline void z8530_write(index_t chan, uint8_t reg, uint8_t val)
48 
{
 91 
{
- 
 
 92 
    /*
- 
 
 93 
     * Registers 8-15 will automatically issue the Point High
- 
 
 94 
     * command as their bit 3 is 1.
- 
 
 95 
     */
- 
 
 96 
    kbd_virt_address[WR0+chan] = reg;   /* select register */
49 
    kbd_virt_address[DATA_REG] = data;
 97 
    kbd_virt_address[WR0+chan] = val;   /* write value */
50 
}
 98 
}
51 
 
 99 
 
52 
static inline uint8_t z8530_data_read(void)
 100 
static inline void z8530_write_a(uint8_t reg, uint8_t val)
- 
 
 101 
{
- 
 
 102 
    z8530_write(Z8530_CHAN_A, reg, val);
- 
 
 103 
}
- 
 
 104 
static inline void z8530_write_b(uint8_t reg, uint8_t val)
53 
{
 105 
{
54 
    return kbd_virt_address[DATA_REG];
 106 
    z8530_write(Z8530_CHAN_B, reg, val);
55 
}
 107 
}
56 
 
 108 
 
57 
static inline uint8_t z8530_status_read(void)
 109 
static inline uint8_t z8530_read(index_t chan, uint8_t reg)
58 
{
 110 
{
- 
 
 111 
    /*
- 
 
 112 
     * Registers 8-15 will automatically issue the Point High
- 
 
 113 
     * command as their bit 3 is 1.
- 
 
 114 
     */
- 
 
 115 
    kbd_virt_address[WR0+chan] = reg;   /* select register */
59 
    return kbd_virt_address[STATUS_REG];
 116 
    return kbd_virt_address[WR0+chan];
60 
}
 117 
}
61 
 
 118 
 
62 
static inline void z8530_command_write(uint8_t command)
 119 
static inline uint8_t z8530_read_a(uint8_t reg)
- 
 
 120 
{
- 
 
 121 
    return z8530_read(Z8530_CHAN_A, reg);
- 
 
 122 
}
- 
 
 123 
static inline uint8_t z8530_read_b(uint8_t reg)
63 
{
 124 
{
64 
    kbd_virt_address[COMMAND_REG] = command;
 125 
    return z8530_read(Z8530_CHAN_B, reg);
65 
}
 126 
}
66 
 
 127 
 
67 
#endif
 128 
#endif
68 
 
 129 
 
69 
/** @}
 130 
/** @}