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Line 55... | Line 55... | ||
55 | #define read_barrier() \ |
55 | #define read_barrier() \ |
56 | asm volatile ("membar #LoadLoad\n" ::: "memory") |
56 | asm volatile ("membar #LoadLoad\n" ::: "memory") |
57 | #define write_barrier() \ |
57 | #define write_barrier() \ |
58 | asm volatile ("membar #StoreStore\n" ::: "memory") |
58 | asm volatile ("membar #StoreStore\n" ::: "memory") |
59 | 59 | ||
- | 60 | static inline void flush(uintptr_t addr) |
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- | 61 | { |
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- | 62 | asm volatile ("flush %0\n" :: "r" (addr) : "memory"); |
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- | 63 | } |
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- | 64 | ||
60 | /** Flush Instruction Memory instruction. */ |
65 | /** Flush Instruction Memory instruction. */ |
61 | static inline void flush(void) |
66 | static inline void flush_blind(void) |
62 | { |
67 | { |
63 | /* |
68 | /* |
64 | * The FLUSH instruction takes address parameter. |
69 | * The FLUSH instruction takes address parameter. |
65 | * As such, it may trap if the address is not found in DTLB. |
70 | * As such, it may trap if the address is not found in DTLB. |
66 | * |
71 | * |
Line 77... | Line 82... | ||
77 | static inline void membar(void) |
82 | static inline void membar(void) |
78 | { |
83 | { |
79 | asm volatile ("membar #Sync\n"); |
84 | asm volatile ("membar #Sync\n"); |
80 | } |
85 | } |
81 | 86 | ||
- | 87 | #define smc_coherence(a) \ |
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- | 88 | { \ |
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- | 89 | write_barrier(); \ |
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- | 90 | flush((a)); \ |
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- | 91 | } |
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- | 92 | ||
82 | #endif |
93 | #endif |
83 | 94 | ||
84 | /** @} |
95 | /** @} |
85 | */ |
96 | */ |