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34 | 34 | ||
35 | #ifndef KERN_sparc64_BARRIER_H_ |
35 | #ifndef KERN_sparc64_BARRIER_H_ |
36 | #define KERN_sparc64_BARRIER_H_ |
36 | #define KERN_sparc64_BARRIER_H_ |
37 | 37 | ||
38 | /* |
38 | /* |
39 | * We assume TSO memory model in which only reads can pass earlier stores |
39 | * Our critical section barriers are prepared for the weakest RMO memory model. |
40 | * (but not earlier reads). Therefore, CS_ENTER_BARRIER() and CS_LEAVE_BARRIER() |
- | |
41 | * can be empty. |
- | |
42 | */ |
40 | */ |
43 | #define CS_ENTER_BARRIER() __asm__ volatile ("" ::: "memory") |
41 | #define CS_ENTER_BARRIER() \ |
- | 42 | __asm__ volatile ( \ |
|
- | 43 | "membar #LoadLoad | #LoadStore\n" \ |
|
- | 44 | ::: "memory" \ |
|
- | 45 | ) |
|
44 | #define CS_LEAVE_BARRIER() __asm__ volatile ("" ::: "memory") |
46 | #define CS_LEAVE_BARRIER() \ |
- | 47 | __asm__ volatile ( \ |
|
- | 48 | "membar #StoreStore\n" \ |
|
- | 49 | "membar #LoadStore\n" \ |
|
- | 50 | ::: "memory" \ |
|
- | 51 | ) |
|
45 | 52 | ||
- | 53 | #define memory_barrier() \ |
|
46 | #define memory_barrier() __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory") |
54 | __asm__ volatile ("membar #LoadLoad | #StoreStore\n" ::: "memory") |
- | 55 | #define read_barrier() \ |
|
47 | #define read_barrier() __asm__ volatile ("membar #LoadLoad\n" ::: "memory") |
56 | __asm__ volatile ("membar #LoadLoad\n" ::: "memory") |
- | 57 | #define write_barrier() \ |
|
48 | #define write_barrier() __asm__ volatile ("membar #StoreStore\n" ::: "memory") |
58 | __asm__ volatile ("membar #StoreStore\n" ::: "memory") |
49 | 59 | ||
50 | /** Flush Instruction Memory instruction. */ |
60 | /** Flush Instruction Memory instruction. */ |
51 | static inline void flush(void) |
61 | static inline void flush(void) |
52 | { |
62 | { |
53 | /* |
63 | /* |