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37 | 37 | ||
38 | /* |
38 | /* |
39 | * Our critical section barriers are prepared for the weakest RMO memory model. |
39 | * Our critical section barriers are prepared for the weakest RMO memory model. |
40 | */ |
40 | */ |
41 | #define CS_ENTER_BARRIER() \ |
41 | #define CS_ENTER_BARRIER() \ |
42 | asm volatile ( \ |
42 | asm volatile ( \ |
43 | "membar #LoadLoad | #LoadStore\n" \ |
43 | "membar #LoadLoad | #LoadStore\n" \ |
44 | ::: "memory" \ |
44 | ::: "memory" \ |
45 | ) |
45 | ) |
46 | #define CS_LEAVE_BARRIER() \ |
46 | #define CS_LEAVE_BARRIER() \ |
47 | asm volatile ( \ |
47 | asm volatile ( \ |
48 | "membar #StoreStore\n" \ |
48 | "membar #StoreStore\n" \ |
49 | "membar #LoadStore\n" \ |
49 | "membar #LoadStore\n" \ |
50 | ::: "memory" \ |
50 | ::: "memory" \ |
51 | ) |
51 | ) |
52 | 52 |