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35 | /* |
35 | /* |
36 | * Switch to BEV normal level so that exception vectors point to the kernel. |
36 | * Switch to BEV normal level so that exception vectors point to the kernel. |
37 | * Clear the error level. |
37 | * Clear the error level. |
38 | */ |
38 | */ |
39 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
39 | cp0_status_write(cp0_status_read() & ~(cp0_status_bev_bootstrap_bit|cp0_status_erl_error_bit)); |
40 | 40 | ||
41 | /* |
41 | /* |
42 | * Unmask hardware clock interrupt. |
42 | * Unmask hardware clock interrupt. |
43 | */ |
43 | */ |
44 | cp0_status_write(cp0_status_read() | (1<<cp0_status_im7_shift)); |
44 | cp0_status_write(cp0_status_read() | (1<<cp0_status_im7_shift)); |
45 | 45 | ||
46 | /* |
46 | /* |
47 | * Start hardware clock. |
47 | * Start hardware clock. |
48 | */ |
48 | */ |
49 | cp0_compare_write(cp0_compare_value); |
49 | cp0_compare_write(cp0_compare_value); |
50 | cp0_count_write(0); |
50 | cp0_count_write(0); |