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34 | 34 | ||
35 | #ifndef KERN_mips32_CP0_H_ |
35 | #ifndef KERN_mips32_CP0_H_ |
36 | #define KERN_mips32_CP0_H_ |
36 | #define KERN_mips32_CP0_H_ |
37 | 37 | ||
38 | #include <arch/types.h> |
38 | #include <arch/types.h> |
39 | #include <arch/mm/tlb.h> |
- | |
40 | 39 | ||
41 | #define cp0_status_ie_enabled_bit (1<<0) |
40 | #define cp0_status_ie_enabled_bit (1 << 0) |
42 | #define cp0_status_exl_exception_bit (1<<1) |
41 | #define cp0_status_exl_exception_bit (1 << 1) |
43 | #define cp0_status_erl_error_bit (1<<2) |
42 | #define cp0_status_erl_error_bit (1 << 2) |
44 | #define cp0_status_um_bit (1<<4) |
43 | #define cp0_status_um_bit (1 << 4) |
45 | #define cp0_status_bev_bootstrap_bit (1<<22) |
44 | #define cp0_status_bev_bootstrap_bit (1 << 22) |
46 | #define cp0_status_fpu_bit (1<<29) |
45 | #define cp0_status_fpu_bit (1 << 29) |
47 | 46 | ||
48 | #define cp0_status_im_shift 8 |
47 | #define cp0_status_im_shift 8 |
49 | #define cp0_status_im_mask 0xff00 |
48 | #define cp0_status_im_mask 0xff00 |
50 | 49 | ||
51 | #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
50 | #define cp0_cause_excno(cause) ((cause >> 2) & 0x1f) |
Line 58... | Line 57... | ||
58 | */ |
57 | */ |
59 | #define cp0_compare_value 100000 |
58 | #define cp0_compare_value 100000 |
60 | 59 | ||
61 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
60 | #define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask)) |
62 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
61 | #define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask) |
63 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it)))) |
62 | #define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1 << (cp0_status_im_shift + (it)))) |
64 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it)))) |
63 | #define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1 << (cp0_status_im_shift + (it)))) |
65 | 64 | ||
66 | #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \ |
65 | #define GEN_READ_CP0(nm,reg) static inline uint32_t cp0_ ##nm##_read(void) \ |
67 | { \ |
66 | { \ |
68 | uint32_t retval; \ |
67 | uint32_t retval; \ |
69 | asm("mfc0 %0, $" #reg : "=r"(retval)); \ |
68 | asm("mfc0 %0, $" #reg : "=r"(retval)); \ |