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#define cp0_status_erl_error_bit    (1<<2)
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#define cp0_status_erl_error_bit    (1<<2)
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#define cp0_status_um_bit           (1<<4)
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#define cp0_status_um_bit           (1<<4)
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#define cp0_status_bev_bootstrap_bit    (1<<22)
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#define cp0_status_bev_bootstrap_bit    (1<<22)
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#define cp0_status_fpu_bit              (1<<29)
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#define cp0_status_fpu_bit              (1<<29)
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#define cp0_status_im7_shift        15
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#define cp0_status_im_shift     8
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#define cp0_status_im_mask              0xff00
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/*
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/*
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 * Magic value for use in msim.
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 * Magic value for use in msim.
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 * On AMD Duron 800Mhz, this roughly seems like one us.
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 * On AMD Duron 800Mhz, this roughly seems like one us.
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 */
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 */
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#define cp0_compare_value       10000
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#define cp0_compare_value       10000
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static inline void tlbwr(void)
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static inline void tlbwr(void)
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{
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{
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    __asm__ volatile ("tlbwr");
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    __asm__ volatile ("tlbwr");
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}
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}
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#define cp0_mask_all_int() cp0_status_write(cp0_status_read() & ~(cp0_status_im_mask))
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#define cp0_unmask_all_int() cp0_status_write(cp0_status_read() | cp0_status_im_mask)
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#define cp0_mask_int(it) cp0_status_write(cp0_status_read() & ~(1<<(cp0_status_im_shift+(it))))
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#define cp0_unmask_int(it) cp0_status_write(cp0_status_read() | (1<<(cp0_status_im_shift+(it))))
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extern  __u32 cp0_index_read(void);
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extern  __u32 cp0_index_read(void);
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extern void cp0_idnex_write(__u32 val);
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extern void cp0_idnex_write(__u32 val);
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