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 */
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 */
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#ifndef __MIPS_ATOMIC_H__
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#ifndef __MIPS_ATOMIC_H__
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#define __MIPS_ATOMIC_H__
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#define __MIPS_ATOMIC_H__
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#define atomic_inc(x)   ((*x)++)
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#define atomic_inc(x)   (a_add(x,1))
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#define atomic_dec(x)   ((*x)--)
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#define atomic_dec(x)   (a_sub(x,1))
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/*
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 * Atomic addition
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 *
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 * This case is harder, and we have to use the special LL and SC operations
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 * to achieve atomicity. The instructions are similar to LW (load) and SW
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 * (store), except that the LL (load-linked) instruction loads the address
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 * of the variable to a special register and if another process writes to
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 * the same location, the SC (store-conditional) instruction fails.
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 */
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static inline int a_add( volatile int *val, int i)
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{
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    int tmp, tmp2;
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    asm volatile (
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        "   .set    push\n"
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        "   .set    noreorder\n"
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        "   nop\n"
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        "1:\n"
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        "   ll  %0, %1\n"
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        "   addu    %0, %0, %2\n"
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        "       move    %3, %0\n"
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        "   sc  %0, %1\n"
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        "   beq %0, 0x0, 1b\n"
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        "   move    %0, %3\n"
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        "   .set    pop\n"
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        : "=&r" (tmp), "=o" (*val)
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        : "r" (i), "r" (tmp2)
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        );
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    return tmp;
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}
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/*
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 * Atomic subtraction
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 *
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 * Implemented in the same manner as a_add, except we substract the value.
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 */
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static inline int a_sub( volatile int *val, int i)
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{
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    int tmp, tmp2;
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    asm volatile (
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        "   .set    push\n"
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        "   .set    noreorder\n"
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        "   nop\n"
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        "1:\n"
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        "   ll  %0, %1\n"
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        "   subu    %0, %0, %2\n"
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        "       move    %3, %0\n"
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        "   sc  %0, %1\n"
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        "   beq %0, 0x0, 1b\n"
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        "       move    %0, %3\n"
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        "   .set    pop\n"
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        : "=&r" (tmp), "=o" (*val)
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        : "r" (i), "r" (tmp2)
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        );
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    return tmp;
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}
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#endif
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#endif