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 * This goal is achieved by using procedure calls after RSE becomes operational.
 44 
 * This goal is achieved by using procedure calls after RSE becomes operational.
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 *
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 *
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 * Some steps are skipped (enabling and disabling interrupts).
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 * Some steps are skipped (enabling and disabling interrupts).
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 * Some steps are not fully supported yet (e.g. interruptions
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 * Some steps are not fully supported yet (e.g. interruptions
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 * from userspace and floating-point context).
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 * from userspace and floating-point context).
- 
 
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 *
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 * @param offs Offset from the beginning of IVT.
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 * @param handler Interrupt handler address.
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 */
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 */
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.macro HEAVYWEIGHT_HANDLER offs handler
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.macro HEAVYWEIGHT_HANDLER offs handler
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    .org IVT + \offs
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    .org IVT + \offs
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    /* 1. copy interrupt registers into bank 0 */
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    /* 1. copy interrupt registers into bank 0 */
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	mov r29 = ar.bsp
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	mov r29 = ar.bsp
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	st8 [r31] = r27, -8	/* save ar.rnat */
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	st8 [r31] = r27, -8	/* save ar.rnat */
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	st8 [r31] = r28, -8	/* save ar.bspstore */
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	st8 [r31] = r28, -8	/* save ar.bspstore */
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	st8 [r31] = r29		/* save ar.bsp */
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	st8 [r31] = r29, -8	/* save ar.bsp */
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	mov ar.rsc = r24	/* restore RSE's setting */
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	mov ar.rsc = r24	/* restore RSE's setting */
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	.explicit
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	.explicit
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    /* the rest of the save-handler can be kept outside IVT */
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    /* the rest of the save-handler can be kept outside IVT */
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	br.ret.sptk.many rp
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	br.ret.sptk.many rp
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.global heavyweight_handler_finalize
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.global heavyweight_handler_finalize
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heavyweight_handler_finalize:
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heavyweight_handler_finalize:
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    /* 16. RSE switch to interrupted context */
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    /* 16. RSE switch to interrupted context */
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 - 
 
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/********************************************************************************************/
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	.auto
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	.auto
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	cover			/*Allocate zerro size frame (Step 1(from Intel Docs))*/
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	cover			/* allocate zerro size frame (step 1 (from Intel Docs)) */
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	add r31 = STACK_SCRATCH_AREA_SIZE, r12
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	add r31 = STACK_SCRATCH_AREA_SIZE, r12
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	mov r28 = ar.bspstore   /*Calculate loadrs (step 2)*/
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	mov r28 = ar.bspstore   /* calculate loadrs (step 2) */
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	ld8 r29 = [r31], +8
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	ld8 r29 = [r31], +8     /* load ar.bsp */
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	sub r27 = r29 , r28
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	sub r27 = r29 , r28
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	shl r27 = r27, 16
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	shl r27 = r27, 16
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	mov r24 = ar.rsc
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	mov r24 = ar.rsc
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	and r30 = ~3, r24
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	and r30 = ~3, r24
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	or  r24 = r30 , r27
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	or  r24 = r30 , r27
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	mov ar.rsc = r24	/* place RSE in enforced lazy mode */
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	mov ar.rsc = r24	/* place RSE in enforced lazy mode */
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- 
 
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	loadrs 			/* (step 3) */
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	ld8 r28 = [r31], +8     /* load ar.bspstore */
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	ld8 r27 = [r31], +8 	/* load ar.rnat */
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	ld8 r26 = [r31], +8 	/* load cr.ifs */
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	ld8 r25 = [r31], +8 	/* load ar.pfs */
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	ld8 r24 = [r31], +8 	/* load ar.rsc */
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- 
 
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	mov ar.bspstore = r28	/* (step 4) */
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	loadrs 			/*(Step 3)*/
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	mov ar.rnat = r27	/* (step 5) */
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 - 
 
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				/*Read saved registers*/
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	ld8 r28 = [r31], +8     /*ar.bspstore*/
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	ld8 r27 = [r31], +8 	/*ar.rnat*/
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	ld8 r26 = [r31], +8 	/*cr.ifs*/
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	ld8 r25 = [r31], +8 	/*ar.pfs*/
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	ld8 r24 = [r31], +8 	/*ar.rsc*/
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	mov ar.bspstore = r28	/*(Step 4)*/
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	mov ar.rnat = r27	/*(Step 5)*/
 - 
 
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 - 
 
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	mov ar.pfs = r25	/*(Step 6)*/
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	mov ar.pfs = r25	/* (step 6) */
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	mov cr.ifs = r26
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	mov cr.ifs = r26
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	mov ar.rsc = r24	/*(Step 7)*/
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	mov ar.rsc = r24	/* (step 7) */
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 - 
 
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	.explicit
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	.explicit
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 - 
 
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/********************************************************************************************/
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    /* 17. restore interruption state from memory stack */
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    /* 17. restore interruption state from memory stack */
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 - 
 
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	ld8 r28 = [r31] , +8 ;;	/* load cr.ifa */
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	ld8 r28 = [r31], +8 ;;	/* load cr.ifa */
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	ld8 r27 = [r31] , +8 ;;	/* load cr.isr */
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	ld8 r27 = [r31], +8 ;;	/* load cr.isr */
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	ld8 r26 = [r31] , +8 ;;	/* load cr.iipa */
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	ld8 r26 = [r31], +8 ;;	/* load cr.iipa */
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	ld8 r25 = [r31] , +8 ;;	/* load cr.ipsr */
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	ld8 r25 = [r31], +8 ;;	/* load cr.ipsr */
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	ld8 r24 = [r31] , +8 ;;	/* load cr.iip */
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	ld8 r24 = [r31], +8 ;;	/* load cr.iip */
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 - 
 
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	mov cr.iip = r24
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	mov cr.iip = r24
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	mov cr.ipsr = r25
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	mov cr.ipsr = r25
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	mov cr.iipa = r26
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	mov cr.iipa = r26
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	mov cr.isr = r27
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	mov cr.isr = r27
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	mov cr.ifa = r28
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	mov cr.ifa = r28
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 - 
 
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- 
 
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    /* 18. restore predicate registers from memory stack */
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    /* 18. restore predicate registers from memory stack */
325 
 
 - 
 
326 
 
 - 
 
327 
	ld8 r29 = [r31] , -8 ;;	/* load predicate registers */
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	ld8 r29 = [r31] , -8 ;;	/* load predicate registers */
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	mov pr =r29 ;;
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	mov pr = r29
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- 
 
330 
	add r12 = STACK_FRAME_SIZE,r12;;
 - 
 
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    /* 19. return from interruption */
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    /* 19. return from interruption */
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    	add r12 = STACK_FRAME_SIZE, r12
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	rfi;;
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	rfi ;;
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 - 
 
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dump_gregs:
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dump_gregs:
337 
mov r16 = REG_DUMP;;
 315 
mov r16 = REG_DUMP;;
338 
st8 [r16] = r0;;
 316 
st8 [r16] = r0;;
339 
add r16 = 8,r16 ;;
 317 
add r16 = 8,r16 ;;