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36 | #ifndef __xen32_ASM_H__ |
36 | #ifndef __xen32_ASM_H__ |
37 | #define __xen32_ASM_H__ |
37 | #define __xen32_ASM_H__ |
38 | 38 | ||
39 | #include <arch/pm.h> |
39 | #include <arch/pm.h> |
40 | #include <arch/types.h> |
40 | #include <arch/types.h> |
- | 41 | #include <arch/barrier.h> |
|
41 | #include <config.h> |
42 | #include <config.h> |
42 | 43 | ||
43 | extern uint32_t interrupt_handler_size; |
44 | extern uint32_t interrupt_handler_size; |
44 | 45 | ||
45 | extern void interrupt_handlers(void); |
46 | extern void interrupt_handlers(void); |
Line 148... | Line 149... | ||
148 | * |
149 | * |
149 | * @return Old interrupt priority level. |
150 | * @return Old interrupt priority level. |
150 | */ |
151 | */ |
151 | static inline ipl_t interrupts_enable(void) |
152 | static inline ipl_t interrupts_enable(void) |
152 | { |
153 | { |
153 | ipl_t v = 0; |
154 | // FIXME SMP |
- | 155 | ||
154 | /* __asm__ volatile ( |
156 | ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask; |
155 | "pushf\n\t" |
157 | write_barrier(); |
156 | "popl %0\n\t" |
158 | shared_info.vcpu_info[0].evtchn_upcall_mask = 0; |
157 | "sti\n" |
159 | write_barrier(); |
- | 160 | if (shared_info.vcpu_info[0].evtchn_upcall_pending) |
|
158 | : "=r" (v) |
161 | force_evtchn_callback(); |
159 | );*/ |
162 | |
160 | return v; |
163 | return v; |
161 | } |
164 | } |
162 | 165 | ||
163 | /** Disable interrupts. |
166 | /** Disable interrupts. |
164 | * |
167 | * |
Line 167... | Line 170... | ||
167 | * |
170 | * |
168 | * @return Old interrupt priority level. |
171 | * @return Old interrupt priority level. |
169 | */ |
172 | */ |
170 | static inline ipl_t interrupts_disable(void) |
173 | static inline ipl_t interrupts_disable(void) |
171 | { |
174 | { |
172 | ipl_t v = 0; |
175 | // FIXME SMP |
- | 176 | ||
173 | /* __asm__ volatile ( |
177 | ipl_t v = shared_info.vcpu_info[0].evtchn_upcall_mask; |
174 | "pushf\n\t" |
- | |
175 | "popl %0\n\t" |
178 | shared_info.vcpu_info[0].evtchn_upcall_mask = 1; |
176 | "cli\n" |
- | |
177 | : "=r" (v) |
179 | write_barrier(); |
178 | );*/ |
180 | |
179 | return v; |
181 | return v; |
180 | } |
182 | } |
181 | 183 | ||
182 | /** Restore interrupt priority level. |
184 | /** Restore interrupt priority level. |
183 | * |
185 | * |
Line 185... | Line 187... | ||
185 | * |
187 | * |
186 | * @param ipl Saved interrupt priority level. |
188 | * @param ipl Saved interrupt priority level. |
187 | */ |
189 | */ |
188 | static inline void interrupts_restore(ipl_t ipl) |
190 | static inline void interrupts_restore(ipl_t ipl) |
189 | { |
191 | { |
190 | /* __asm__ volatile ( |
192 | if (ipl == 0) |
191 | "pushl %0\n\t" |
193 | interrupts_enable(); |
192 | "popf\n" |
194 | else |
193 | : : "r" (ipl) |
195 | interrupts_disable(); |
194 | );*/ |
- | |
195 | } |
196 | } |
196 | 197 | ||
197 | /** Return interrupt priority level. |
198 | /** Return interrupt priority level. |
198 | * |
199 | * |
199 | * @return EFLAFS. |
200 | * @return EFLAFS. |
200 | */ |
201 | */ |
201 | static inline ipl_t interrupts_read(void) |
202 | static inline ipl_t interrupts_read(void) |
202 | { |
203 | { |
203 | ipl_t v = 0; |
- | |
204 | /* __asm__ volatile ( |
- | |
205 | "pushf\n\t" |
- | |
206 | "popl %0\n" |
- | |
207 | : "=r" (v) |
204 | // FIXME SMP |
208 | );*/ |
205 | |
209 | return v; |
206 | return shared_info.vcpu_info[0].evtchn_upcall_mask; |
210 | } |
207 | } |
211 | 208 | ||
212 | /** Return base address of current stack |
209 | /** Return base address of current stack |
213 | * |
210 | * |
214 | * Return the base address of the current stack. |
211 | * Return the base address of the current stack. |