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Rev 15 | Rev 125 | ||
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Line 81... | Line 81... | ||
81 | outb(CLK_PORT4, 0x30); |
81 | outb(CLK_PORT4, 0x30); |
82 | outb(CLK_PORT1, 0xff); |
82 | outb(CLK_PORT1, 0xff); |
83 | outb(CLK_PORT1, 0xff); |
83 | outb(CLK_PORT1, 0xff); |
84 | 84 | ||
85 | do { |
85 | do { |
86 | /* will read both status and count */ |
86 | /* will read both status and count */ |
87 | outb(CLK_PORT4, 0xc2); |
87 | outb(CLK_PORT4, 0xc2); |
88 | not_ok = (inb(CLK_PORT1)>>6)&1; |
88 | not_ok = (inb(CLK_PORT1)>>6)&1; |
89 | t1 = inb(CLK_PORT1); |
89 | t1 = inb(CLK_PORT1); |
90 | t1 |= inb(CLK_PORT1) << 8; |
90 | t1 |= inb(CLK_PORT1) << 8; |
91 | } while (not_ok); |
91 | } while (not_ok); |
Line 107... | Line 107... | ||
107 | 107 | ||
108 | outb(CLK_PORT4, 0xd2); |
108 | outb(CLK_PORT4, 0xd2); |
109 | o2 = inb(CLK_PORT1); |
109 | o2 = inb(CLK_PORT1); |
110 | o2 |= inb(CLK_PORT1) << 8; |
110 | o2 |= inb(CLK_PORT1) << 8; |
111 | 111 | ||
112 | - | ||
113 | CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + |
112 | CPU->delay_loop_const = ((MAGIC_NUMBER*LOOPS)/1000) / ((t1-t2)-(o1-o2)) + (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0); |
114 | (((MAGIC_NUMBER*LOOPS)/1000) % ((t1-t2)-(o1-o2)) ? 1 : 0); |
- | |
115 | - | ||
116 | 113 | ||
117 | clk1 = rdtsc(); |
114 | clk1 = rdtsc(); |
118 | delay(1<<SHIFT); |
115 | delay(1<<SHIFT); |
119 | clk2 = rdtsc(); |
116 | clk2 = rdtsc(); |
120 | 117 |