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#ifndef __sparc64_TLB_H__
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#ifndef __sparc64_TLB_H__
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#define __sparc64_TLB_H__
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#define __sparc64_TLB_H__
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#include <arch/mm/tte.h>
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#include <arch/mm/tte.h>
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#include <arch/mm/mmu.h>
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#include <arch/mm/page.h>
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#include <arch/mm/page.h>
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#include <arch/asm.h>
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#include <arch/asm.h>
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#include <arch/barrier.h>
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#include <arch/barrier.h>
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#include <arch/types.h>
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#include <arch/types.h>
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#include <typedefs.h>
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#include <typedefs.h>
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#define ITLB_ENTRY_COUNT        64
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#define ITLB_ENTRY_COUNT        64
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#define DTLB_ENTRY_COUNT        64
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#define DTLB_ENTRY_COUNT        64
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/** I-MMU ASIs. */
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/** Page sizes. */
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#define ASI_IMMU            0x50
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#define PAGESIZE_8K 0
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#define ASI_IMMU_TSB_8KB_PTR_REG    0x51   
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#define ASI_IMMU_TSB_64KB_PTR_REG   0x52
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#define ASI_ITLB_DATA_IN_REG        0x54
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#define ASI_ITLB_DATA_ACCESS_REG    0x55
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#define ASI_ITLB_TAG_READ_REG       0x56
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#define ASI_IMMU_DEMAP          0x57
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#define PAGESIZE_64K    1
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/** Virtual Addresses within ASI_IMMU. */
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#define VA_IMMU_TAG_TARGET      0x0 /**< IMMU tag target register. */
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#define VA_IMMU_SFSR            0x18    /**< IMMU sync fault status register. */
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#define VA_IMMU_TSB_BASE        0x28    /**< IMMU TSB base register. */
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#define VA_IMMU_TAG_ACCESS      0x30    /**< IMMU TLB tag access register. */
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/** D-MMU ASIs. */
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#define ASI_DMMU            0x58
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#define PAGESIZE_512K   2
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#define ASI_DMMU_TSB_8KB_PTR_REG    0x59   
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#define ASI_DMMU_TSB_64KB_PTR_REG   0x5a
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#define ASI_DMMU_TSB_DIRECT_PTR_REG 0x5b
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#define ASI_DTLB_DATA_IN_REG        0x5c
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#define ASI_DTLB_DATA_ACCESS_REG    0x5d
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#define ASI_DTLB_TAG_READ_REG       0x5e
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#define ASI_DMMU_DEMAP          0x5f
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#define PAGESIZE_4M 3
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/** Virtual Addresses within ASI_DMMU. */
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#define VA_DMMU_TAG_TARGET      0x0 /**< DMMU tag target register. */
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#define VA_PRIMARY_CONTEXT_REG      0x8 /**< DMMU primary context register. */
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#define VA_SECONDARY_CONTEXT_REG    0x10    /**< DMMU secondary context register. */
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#define VA_DMMU_SFSR            0x18    /**< DMMU sync fault status register. */
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#define VA_DMMU_SFAR            0x20    /**< DMMU sync fault address register. */
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#define VA_DMMU_TSB_BASE        0x28    /**< DMMU TSB base register. */
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#define VA_DMMU_TAG_ACCESS      0x30    /**< DMMU TLB tag access register. */
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#define VA_DMMU_VA_WATCHPOINT_REG   0x38    /**< DMMU VA data watchpoint register. */
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#define VA_DMMU_PA_WATCHPOINT_REG   0x40    /**< DMMU PA data watchpoint register. */
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/** I-/D-TLB Data In/Access Register type. */
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/** I-/D-TLB Data In/Access Register type. */
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typedef tte_data_t tlb_data_t;
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typedef tte_data_t tlb_data_t;
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/** I-/D-TLB Data Access Address in Alternate Space. */
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/** I-/D-TLB Data Access Address in Alternate Space. */