WebSVN – HelenOS-historic – Diff – /kernel/trunk/arch/mips32/src/mm/tlb.c



 
static void tlb_refill_fail(istate_t *istate);
static void tlb_invalid_fail(istate_t *istate);
static void tlb_modified_fail(istate_t *istate);
 
static pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc);
 
static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
 
/** Initialize TLB
 *
 * Initialize TLB.
 * Invalidate all entries and mark wired entries.

void tlb_refill(istate_t *istate)
{
    entry_lo_t lo;
    entry_hi_t hi;
    asid_t asid;
    uintptr_t badvaddr;
    pte_t *pte;
    int pfrc;
 
    badvaddr = cp0_badvaddr_read();
 

 * @param istate Interrupted register context.
 */
void tlb_invalid(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 

 * @param istate Interrupted register context.
 */
void tlb_modified(istate_t *istate)
{
    tlb_index_t index;
    uintptr_t badvaddr;
    entry_lo_t lo;
    entry_hi_t hi;
    pte_t *pte;
    int pfrc;
 

 * @param istate Pointer to interrupted state.
 * @param pfrc Pointer to variable where as_page_fault() return code will be stored.
 *
 * @return PTE on success, NULL otherwise.
 */
pte_t *find_mapping_and_check(uintptr_t badvaddr, int access, istate_t *istate, int *pfrc)
{
    entry_hi_t hi;
    pte_t *pte;
 
    hi.value = cp0_entry_hi_read();

        }
       
    }
}
 
void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
{
    lo->value = 0;
    lo->g = g;
    lo->v = v;
    lo->d = d;
    lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
    lo->pfn = pfn;
}
 
void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
{
    hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
    hi->asid = asid;
}
 

 *
 * @param asid Address space identifier.
 * @param page First page whose TLB entry is to be invalidated.
 * @param cnt Number of entries to invalidate.
 */
void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
{
    int i;
    ipl_t ipl;
    entry_lo_t lo0, lo1;
    entry_hi_t hi, hi_save;

Rev 1776	Rev 1780
Line 49...	Line 49...
49		49
50	static void tlb_refill_fail(istate_t *istate);	50	static void tlb_refill_fail(istate_t *istate);
51	static void tlb_invalid_fail(istate_t *istate);	51	static void tlb_invalid_fail(istate_t *istate);
52	static void tlb_modified_fail(istate_t *istate);	52	static void tlb_modified_fail(istate_t *istate);
53		53
54	static pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc);	54	static pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc);
55		55
56	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn);	56	static void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn);
57	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr);	57	static void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr);
58		58
59	/** Initialize TLB	59	/** Initialize TLB
60	*	60	*
61	* Initialize TLB.	61	* Initialize TLB.
62	* Invalidate all entries and mark wired entries.	62	* Invalidate all entries and mark wired entries.
Line 94...	Line 94...
94	void tlb_refill(istate_t *istate)	94	void tlb_refill(istate_t *istate)
95	{	95	{
96	entry_lo_t lo;	96	entry_lo_t lo;
97	entry_hi_t hi;	97	entry_hi_t hi;
98	asid_t asid;	98	asid_t asid;
99	__address badvaddr;	99	uintptr_t badvaddr;
100	pte_t *pte;	100	pte_t *pte;
101	int pfrc;	101	int pfrc;
102		102
103	badvaddr = cp0_badvaddr_read();	103	badvaddr = cp0_badvaddr_read();
104		104
Line 164...	Line 164...
164	* @param istate Interrupted register context.	164	* @param istate Interrupted register context.
165	*/	165	*/
166	void tlb_invalid(istate_t *istate)	166	void tlb_invalid(istate_t *istate)
167	{	167	{
168	tlb_index_t index;	168	tlb_index_t index;
169	__address badvaddr;	169	uintptr_t badvaddr;
170	entry_lo_t lo;	170	entry_lo_t lo;
171	entry_hi_t hi;	171	entry_hi_t hi;
172	pte_t *pte;	172	pte_t *pte;
173	int pfrc;	173	int pfrc;
174		174
Line 248...	Line 248...
248	* @param istate Interrupted register context.	248	* @param istate Interrupted register context.
249	*/	249	*/
250	void tlb_modified(istate_t *istate)	250	void tlb_modified(istate_t *istate)
251	{	251	{
252	tlb_index_t index;	252	tlb_index_t index;
253	__address badvaddr;	253	uintptr_t badvaddr;
254	entry_lo_t lo;	254	entry_lo_t lo;
255	entry_hi_t hi;	255	entry_hi_t hi;
256	pte_t *pte;	256	pte_t *pte;
257	int pfrc;	257	int pfrc;
258		258
Line 381...	Line 381...
381	* @param istate Pointer to interrupted state.	381	* @param istate Pointer to interrupted state.
382	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.	382	* @param pfrc Pointer to variable where as_page_fault() return code will be stored.
383	*	383	*
384	* @return PTE on success, NULL otherwise.	384	* @return PTE on success, NULL otherwise.
385	*/	385	*/
386	pte_t find_mapping_and_check(__address badvaddr, int access, istate_t istate, int *pfrc)	386	pte_t find_mapping_and_check(uintptr_t badvaddr, int access, istate_t istate, int *pfrc)
387	{	387	{
388	entry_hi_t hi;	388	entry_hi_t hi;
389	pte_t *pte;	389	pte_t *pte;
390		390
391	hi.value = cp0_entry_hi_read();	391	hi.value = cp0_entry_hi_read();
Line 443...	Line 443...
443	}	443	}
444		444
445	}	445	}
446	}	446	}
447		447
448	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, __address pfn)	448	void prepare_entry_lo(entry_lo_t *lo, bool g, bool v, bool d, bool cacheable, uintptr_t pfn)
449	{	449	{
450	lo->value = 0;	450	lo->value = 0;
451	lo->g = g;	451	lo->g = g;
452	lo->v = v;	452	lo->v = v;
453	lo->d = d;	453	lo->d = d;
454	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;	454	lo->c = cacheable ? PAGE_CACHEABLE_EXC_WRITE : PAGE_UNCACHED;
455	lo->pfn = pfn;	455	lo->pfn = pfn;
456	}	456	}
457		457
458	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, __address addr)	458	void prepare_entry_hi(entry_hi_t *hi, asid_t asid, uintptr_t addr)
459	{	459	{
460	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);	460	hi->value = ALIGN_DOWN(addr, PAGE_SIZE * 2);
461	hi->asid = asid;	461	hi->asid = asid;
462	}	462	}
463		463
Line 565...	Line 565...
565	*	565	*
566	* @param asid Address space identifier.	566	* @param asid Address space identifier.
567	* @param page First page whose TLB entry is to be invalidated.	567	* @param page First page whose TLB entry is to be invalidated.
568	* @param cnt Number of entries to invalidate.	568	* @param cnt Number of entries to invalidate.
569	*/	569	*/
570	void tlb_invalidate_pages(asid_t asid, __address page, count_t cnt)	570	void tlb_invalidate_pages(asid_t asid, uintptr_t page, count_t cnt)
571	{	571	{
572	int i;	572	int i;
573	ipl_t ipl;	573	ipl_t ipl;
574	entry_lo_t lo0, lo1;	574	entry_lo_t lo0, lo1;
575	entry_hi_t hi, hi_save;	575	entry_hi_t hi, hi_save;

Subversion Repositories HelenOS-historic

(root)/kernel/trunk/arch/mips32/src/mm/tlb.c @ 1078 – Rev 1776 → 1780